[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Renato Golin]

On 27 March 2013 17:14, Måns Rullgård <mans at mansr.com> wrote:

> That is correct in some sense.  The GNU assembler allows a single
> register with ldrd and friends, the second one in this case being
> implicitly one higher (as in the ARM instruction encoding).
>

Mans,

Why don't you produce a list of inline assembly syntaxes you would like to
see and we can pick the ones that make sense for LLVM?

I don't really want to go down the road of supporting every GCC
idiosyncrasy, but would be good to support the general rule, especially one
that has been seen on the Linux kernel.

cheers,
--renato
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