[LLVMdev] Problems with 64-bit register operands of inline asm on ARM

[Måns Rullgård]

Renato Golin <renato.golin at linaro.org> writes:

> On 27 March 2013 17:14, Måns Rullgård <mans at mansr.com> wrote:
>
>> That is correct in some sense.  The GNU assembler allows a single
>> register with ldrd and friends, the second one in this case being
>> implicitly one higher (as in the ARM instruction encoding).
>>
>
> Mans,
>
> Why don't you produce a list of inline assembly syntaxes you would like to
> see and we can pick the ones that make sense for LLVM?

I don't have an exhaustive list of things gcc allows by design or
accident, but here's something I wrote up a while back:
http://hardwarebug.org/2010/07/06/arm-inline-asm-secrets/

> I don't really want to go down the road of supporting every GCC
> idiosyncrasy, but would be good to support the general rule, especially one
> that has been seen on the Linux kernel.

The trouble is that there are very few actual rules.  To do anything
useful, you're more or less required to use undocumented features.  The
best we can do is probably to compile as much code as possible and fix
whatever we find that's broken.

In the long term, I'd like to see people moving away from inline
assembly entirely, and I do what I can to discourage its use.

-- 
Måns Rullgård
mans at mansr.com