[llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM

Weiming Zhao weimingz at codeaurora.org
Wed Dec 5 11:39:53 PST 2012


Hi Jakob,

 

I tried your suggestion for ldrexd of inlineasm. It works now. Could you
please check my steps below and see if I'm on the right track:

 

1.       In DAG selection for inlineAsm, I use createGPRPairNode() instead
of createVirtualRegister() to replace the original two GPRs. The use of the
original two GPRs are replaced with Extract_Subreg node. So the code would
be like:

Vreg0 = REG_SEQUENCE(..);  INLNEASM (. VReg0);  Vreg1 = Extract_subreg
vreg0, idx_0; .

 

2.       I have to fix INLINEASM case of InstrEmitter::EmitSpecialNode() to
let it accept a REG_SEQUENCE node as well. Currently, it only expects a
RegisterSDNode for InlineAsm::Kind_RegDefEarlyClobber/Kind_Clobber.

 

3.         I have to fix InstrEmitter::EmitSubregNode by changing
"MachineInstr *DefMI = MRI->getVRegDef(VReg)" to "MachineInstr *DefMI =
MRI->getUniqueVRegDef(VReg)". The reason is vreg0 is defined by both
REQ_Sequence and InlineAsm. 

 

4.       I have to fix InstrEmitter::EmitSpecialNode() to let CopyFromReg
accepts a Extract_subreg SDNode. 

 

Thanks,

Weiming

 

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Tuesday, December 04, 2012 3:20 PM
To: weimingz at codeaurora.org; Zhao
Cc: Evan Cheng; llvm-commits at cs.uiuc.edu; grosbach at apple.com
Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm
with 64-bit data on ARM

 

 

On Dec 4, 2012, at 2:56 PM, "Weiming Zhao" <weimingz at codeaurora.org> wrote:





Yes, I tried to follow the similar approach in this patch.

But ldrexd/strexd intrinsic are handled differently

 

No, you just wrote the code yourself to handle Intrinsic::arm_ldrexd and
Intrinsic::arm_strexd.

 

So for InlineASM DAG, I also tried to create a VR first. The order of VR
creation  should be handled by glue edges.

 

You are thinking of the atomic pseudo-instructions which are expanded after
instruction selection.

 

/jakob

 

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