[llvm-commits] [llvm] r162012 - /llvm/trunk/lib/Target/X86/X86.td

[Craig Topper]

--- test/CodeGen/X86/fma.ll    (revision 162188)
+++ test/CodeGen/X86/fma.ll    (working copy)
@@ -2,6 +2,10 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin10               | FileCheck %s
--check-prefix=CHECK-FMA-CALL
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma | FileCheck %s
--check-prefix=CHECK-FMA-INST
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10             | FileCheck %s
--check-prefix=CHECK-FMA-CALL
+; RUN: llc < %s -mcpu=bdver2 -mattr=+fma  | FileCheck %s
--check-prefix=CHECK-FMA-INST
+; RUN: llc < %s -mcpu=bdver2 | FileCheck %s --check-prefix=CHECK-FMA-CALL
+; RUN: llc < %s -mcpu=bdver2 -mattr=+fma | FileCheck %s
--check-prefix=CHECK-FMA-INST
+; RUN: llc < %s -mcpu=bdver2 | FileCheck %s --check-prefix=CHECK-FMA-CALL

The last 2 lines are the same as the previous 2 lines. Did you intend to
make one 64-bit and one 32-bit as was done for the original cases?
Also you don't need +fma for the cases where you want fma instructions.
cpu=bdver2 takes care of that and that's what you're trying to test. You
should add "-fma4" for CHECK-FMA-INST. For the CHECK-FMA-CALL versions you
need to disable fma and fma4.

While you're in this test can you fix up the original versions to have
-mattr=-fma,-fma4 on the FMA-CALL versions and -mattr=+fma,-fma4 on the
FMA-INST versions. As they are right now they'll break if the machine that
runs the test is a Haswell or Bulldozer since there is no explicit cpu
selected.

--- test/CodeGen/X86/fma_patterns.ll    (revision 162188)
+++ test/CodeGen/X86/fma_patterns.ll    (working copy)
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2
-mattr=avx2,+fma -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mcpu=bdver2 -mattr=fma -fp-contract=fast | FileCheck %s

Again you don't want -mattr=fma, you're trying to test that bdver2 implies
fma. But explicitly disable fma4.

--- test/CodeGen/X86/fma4-intrinsics-x86_64.ll    (revision 162188)
+++ test/CodeGen/X86/fma4-intrinsics-x86_64.ll    (working copy)
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64
-mattr=+avx,+fma4 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2
-mattr=+avx,+fma4,-fma | FileCheck %s

Just use -mattr=-fma for the bdver2.

On Sun, Aug 19, 2012 at 10:46 AM, Anitha Boyapati <anitha.boyapati at gmail.com
> wrote:

>
>
> On 17 August 2012 04:20, Rafael Espíndola <rafael.espindola at gmail.com>wrote:
>
>> Can you add a test for this?
>>
>>
>>
>
> Attached patch tests agressive FMA  formation and intrinsics for bdver2
> target. I have noticed 2 issues:
>
> 1.  In fma4-intrinsics-x86_64.ll, I had to explicitly disable FMA3 until
> I fix that. (This issue was noticed during review)
> 2. test/CodeGen/X86/fma3-intrinsics.ll fails for one case for bdver2
> because memory form of FMA is not generated. (CHECK for memory pattern in @test_x86_fmadd_ps_y).
> Since this is not an actual failure, I need to fix the CHECK pattern.
>
> -Anitha
>
>
>
>
>>  On 16 August 2012 00:04, Anitha Boyapati <anitha.boyapati at gmail.com>
>> wrote:
>> > Author: anithab
>> > Date: Wed Aug 15 23:04:02 2012
>> > New Revision: 162012
>> >
>> > URL: http://llvm.org/viewvc/llvm-project?rev=162012&view=rev
>> > Log:
>> > Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as
>> well.
>> >
>> > Modified:
>> >     llvm/trunk/lib/Target/X86/X86.td
>> >
>> > Modified: llvm/trunk/lib/Target/X86/X86.td
>> > URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=162012&r1=162011&r2=162012&view=diff
>> >
>> ==============================================================================
>> > --- llvm/trunk/lib/Target/X86/X86.td (original)
>> > +++ llvm/trunk/lib/Target/X86/X86.td Wed Aug 15 23:04:02 2012
>> > @@ -97,7 +97,7 @@
>> >                                        [FeatureAVX, FeatureSSE4A]>;
>> >  def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
>> >                                        "Enable XOP instructions",
>> > -                                      [FeatureAVX, FeatureSSE4A]>;
>> > +                                      [FeatureFMA4]>;
>> >  def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
>> >                                            "HasVectorUAMem", "true",
>> >                   "Allow unaligned memory operands on vector/SIMD
>> instructions">;
>> > @@ -226,7 +226,7 @@
>> >  def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4,
>> FeatureCMPXCHG16B,
>> >                                 FeatureAES, FeaturePCLMUL,
>> >                                 FeatureF16C, FeatureLZCNT,
>> > -                               FeaturePOPCNT, FeatureBMI]>;
>> > +                               FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
>> >
>> >  def : Proc<"winchip-c6",      [FeatureMMX]>;
>> >  def : Proc<"winchip2",        [Feature3DNow]>;
>> >
>> >
>> > _______________________________________________
>> > llvm-commits mailing list
>> > llvm-commits at cs.uiuc.edu
>> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
>
>
> --
> * Anitha*
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


-- 
~Craig
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