--- test/CodeGen/X86/fma.ll (revision 162188)<br>+++ test/CodeGen/X86/fma.ll (working copy)<br>@@ -2,6 +2,10 @@<br> ; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s --check-prefix=CHECK-FMA-CALL<br>
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma | FileCheck %s --check-prefix=CHECK-FMA-INST<br> ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK-FMA-CALL<br>
+; RUN: llc < %s -mcpu=bdver2 -mattr=+fma | FileCheck %s --check-prefix=CHECK-FMA-INST<br>+; RUN: llc < %s -mcpu=bdver2 | FileCheck %s --check-prefix=CHECK-FMA-CALL<br>+; RUN: llc < %s -mcpu=bdver2 -mattr=+fma | FileCheck %s --check-prefix=CHECK-FMA-INST<br>
+; RUN: llc < %s -mcpu=bdver2 | FileCheck %s --check-prefix=CHECK-FMA-CALL<br><br>The last 2 lines are the same as the previous 2 lines. Did you intend to make one 64-bit and one 32-bit as was done for the original cases?<br>
Also you don't need +fma for the cases where you want fma instructions. cpu=bdver2 takes care of that and that's what you're trying to test. You should add "-fma4" for CHECK-FMA-INST. For the CHECK-FMA-CALL versions you need to disable fma and fma4.<br>
<br>While you're in this test can you fix up the original versions to have -mattr=-fma,-fma4 on the FMA-CALL versions and -mattr=+fma,-fma4 on the FMA-INST versions. As they are right now they'll break if the machine that runs the test is a Haswell or Bulldozer since there is no explicit cpu selected.<br>
<br>--- test/CodeGen/X86/fma_patterns.ll (revision 162188)<br>+++ test/CodeGen/X86/fma_patterns.ll (working copy)<br>@@ -1,4 +1,5 @@<br> ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=avx2,+fma -fp-contract=fast | FileCheck %s<br>
+; RUN: llc < %s -mcpu=bdver2 -mattr=fma -fp-contract=fast | FileCheck %s<br><br>Again you don't want -mattr=fma, you're trying to test that bdver2 implies fma. But explicitly disable fma4.<br><br>--- test/CodeGen/X86/fma4-intrinsics-x86_64.ll (revision 162188)<br>
+++ test/CodeGen/X86/fma4-intrinsics-x86_64.ll (working copy)<br>@@ -1,4 +1,5 @@<br> ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=+avx,+fma4 | FileCheck %s<br>+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=+avx,+fma4,-fma | FileCheck %s<br>
<br>Just use -mattr=-fma for the bdver2.<br><br><div class="gmail_quote">On Sun, Aug 19, 2012 at 10:46 AM, Anitha Boyapati <span dir="ltr"><<a href="mailto:anitha.boyapati@gmail.com" target="_blank">anitha.boyapati@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br><br><div class="gmail_quote"><div class="im">On 17 August 2012 04:20, Rafael Espíndola <span dir="ltr"><<a href="mailto:rafael.espindola@gmail.com" target="_blank">rafael.espindola@gmail.com</a>></span> wrote:<br>
<blockquote style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid" class="gmail_quote">
<p>Can you add a test for this?</p><p> </p></blockquote><div> </div></div><div>Attached patch tests agressive FMA formation and intrinsics for bdver2 target. I have noticed 2 issues:</div><div> </div><div>1. In <span lang="EN">fma4-intrinsics-x86_64.ll, I had to explicitly disable FMA3 until I fix that. (This issue was noticed during review)</span></div>
<div><span lang="EN">2. test/CodeGen/X86/fma3-intrinsics.ll fails for one case for bdver2 because memory form of FMA is not generated. (CHECK for memory pattern in @<span lang="EN">test_x86_fmadd_ps_y). Since this is not an actual failure, I need to fix the CHECK pattern.</span></span></div>
<div><span lang="EN"><span lang="EN"></span></span> </div><div><span lang="EN"><span lang="EN">-Anitha</span></span></div><div><div class="h5"><div> </div><div> </div><div> </div><blockquote style="margin:0px 0px 0px 0.8ex;padding-left:1ex;border-left-color:rgb(204,204,204);border-left-width:1px;border-left-style:solid" class="gmail_quote">
<div><div>
On 16 August 2012 00:04, Anitha Boyapati <<a href="mailto:anitha.boyapati@gmail.com" target="_blank">anitha.boyapati@gmail.com</a>> wrote:<br>
> Author: anithab<br>
> Date: Wed Aug 15 23:04:02 2012<br>
> New Revision: 162012<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=162012&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=162012&view=rev</a><br>
> Log:<br>
> Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=162012&r1=162011&r2=162012&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=162012&r1=162011&r2=162012&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86.td Wed Aug 15 23:04:02 2012<br>
> @@ -97,7 +97,7 @@<br>
> [FeatureAVX, FeatureSSE4A]>;<br>
> def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",<br>
> "Enable XOP instructions",<br>
> - [FeatureAVX, FeatureSSE4A]>;<br>
> + [FeatureFMA4]>;<br>
> def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",<br>
> "HasVectorUAMem", "true",<br>
> "Allow unaligned memory operands on vector/SIMD instructions">;<br>
> @@ -226,7 +226,7 @@<br>
> def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,<br>
> FeatureAES, FeaturePCLMUL,<br>
> FeatureF16C, FeatureLZCNT,<br>
> - FeaturePOPCNT, FeatureBMI]>;<br>
> + FeaturePOPCNT, FeatureBMI, FeatureFMA]>;<br>
><br>
> def : Proc<"winchip-c6", [FeatureMMX]>;<br>
> def : Proc<"winchip2", [Feature3DNow]>;<br>
><br>
><br>
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</div></div></blockquote></div></div></div><span class="HOEnZb"><font color="#888888"><br><br clear="all"><br>-- <br><i style="font-family:times new roman,serif"><b> Anitha</b></i><br><br>
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<br></blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>