[llvm-commits] Patch: new backend for Hexagon processor

[Tony Linthicum]

On 12/9/2011 1:06 PM, Jakob Stoklund Olesen wrote:
>
> On Dec 9, 2011, at 10:28 AM, Tony Linthicum wrote:
>
>>> +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h
>>>
>>> +#define HEXAGON_RESERVED_REG_1 Hexagon::R10
>>> +#define HEXAGON_RESERVED_REG_2 Hexagon::R11
>>>
>>> Hmm. Does that have to go in a header file? Have you looked into using the register scavenger instead of reserving registers?
>>>
>>
>> We are actually currently working on utilizing the register scavenger for this instead.  Can we submit that later when it is done?
>
> Sure.
>
> This is for spilling predicates, right? Hal is fighting the same problem over in the PowerPC target.
>
> /jakob
>

Yep, it's for spilling predicate registers.  There are no loads or 
stores that directly access predicates.  They must be moved to/from 
general purpose registers.

Tony

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