[llvm-commits] Patch: new backend for Hexagon processor

[Hal Finkel]

On Fri, 2011-12-09 at 13:41 -0600, Tony Linthicum wrote:
> On 12/9/2011 1:06 PM, Jakob Stoklund Olesen wrote:
> >
> > On Dec 9, 2011, at 10:28 AM, Tony Linthicum wrote:
> >
> >>> +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h
> >>>
> >>> +#define HEXAGON_RESERVED_REG_1 Hexagon::R10
> >>> +#define HEXAGON_RESERVED_REG_2 Hexagon::R11
> >>>
> >>> Hmm. Does that have to go in a header file? Have you looked into using the register scavenger instead of reserving registers?
> >>>
> >>
> >> We are actually currently working on utilizing the register scavenger for this instead.  Can we submit that later when it is done?
> >
> > Sure.
> >
> > This is for spilling predicates, right? Hal is fighting the same problem over in the PowerPC target.
> >
> > /jakob
> >
> 
> Yep, it's for spilling predicate registers.  There are no loads or 
> stores that directly access predicates.  They must be moved to/from 
> general purpose registers.

As Jakob pointed out to me, the core problem is that the current
register scavenger implementation will only give you one register; for
the PowerPC case, and it looks like for your case as well, we might
really need two registers. In the short term, a reasonable solution
might be to modify the register scavenger to enable it to return
multiple registers. This seems to be related to the number of emergency
spill slots the scavenger reserves (because it "cannot fail"), so there
might be some downside to this. We would have to add some
target-dependent callback to tell the register scavenger how many slots
to reserve (the default would be 1). Do you think that this is worth
doing?

 -Hal

> 
> Tony
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory