[llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h

[Gabor Greif]

Ugh, added the 64-bit version, that won't help you on ARM :-(

Here is 32-bit:

#############################
; *** IR Dump After Optimize for code generation ***

%struct.Foo = type { i8* }

define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc)
nounwind readonly align 2 {
entry:
  %scevgep = getelementptr %struct.Foo* %this, i32 1 ; <%struct.Foo*>
[#uses=1]
  br label %tailrecurse

tailrecurse:                                      ; preds = %sw.bb,
%entry
  %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep,
%entry ] ; <%struct.Foo*> [#uses=3]
  %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] ; <i32>
[#uses=2]
  %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] ; <i32>
[#uses=2]
  %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** ; <i8**> [#uses=1]
  %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1 ; <i8**> [#uses=1]
  %tmp2 = load i8** %scevgep5                     ; <i8*> [#uses=1]
  %0 = ptrtoint i8* %tmp2 to i32                  ; <i32> [#uses=1]
  %and = and i32 %0, 3                            ; <i32> [#uses=3]
  %tst = icmp eq i32 %and, 0                      ; <i1> [#uses=1]
  br i1 %tst, label %sw.bb, label %tailrecurse.switch

tailrecurse.switch:                               ; preds =
%tailrecurse
  switch i32 %and, label %sw.epilog [
    i32 1, label %sw.bb
    i32 3, label %sw.bb6
    i32 2, label %sw.bb8
  ]

sw.bb:                                            ; preds =
%tailrecurse.switch, %tailrecurse
  %shl = shl i32 %acc.tr, 1                       ; <i32> [#uses=1]
  %or = or i32 %and, %shl                         ; <i32> [#uses=1]
  %lsr.iv.next = add i32 %lsr.iv, 1               ; <i32> [#uses=1]
  %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1 ; <
%struct.Foo*> [#uses=1]
  br label %tailrecurse

sw.bb6:                                           ; preds =
%tailrecurse.switch
  ret %struct.Foo* %lsr.iv2

sw.bb8:                                           ; preds =
%tailrecurse.switch
  %tmp1 = add i32 %acc.tr, %lsr.iv                ; <i32> [#uses=1]
  %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1 ; <
%struct.Foo*> [#uses=1]
  ret %struct.Foo* %add.ptr11

sw.epilog:                                        ; preds =
%tailrecurse.switch
  ret %struct.Foo* undef
}
#############################


On 11 Sep., 09:49, Gabor Greif <ggr... at gmail.com> wrote:
> Bill,
>
> you might be interested in my dabbling attempts
> withhttp://llvm.org/bugs/show_bug.cgi?id=8125
> The x86 peephole already manages to eliminate
> the test after the 'and', It would be interesting
> to see whether ARM does too.
> Btw., my commit is not really restricted to 'and',
> any operation that sets the zero flag will do.
>