[llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h

[Bill Wendling]

On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote:

> Bill,
> 
> you might be interested in my dabbling attempts
> with http://llvm.org/bugs/show_bug.cgi?id=8125
> The x86 peephole already manages to eliminate
> the test after the 'and', It would be interesting
> to see whether ARM does too.
> Btw., my commit is not really restricted to 'and',
> any operation that sets the zero flag will do.
> 
> A.t.m. (before your changes) I got:
> LBB0_1:                                 @ %tailrecurse
>                                        @ =>This Inner Loop Header:
> Depth=1
>        ldr     lr, [r2, #-4]
>        and     r4, lr, #3
>        tst     lr, #3
>        beq     LBB0_4
> 
I saw your patch go through. As with your other code, I don't understand it fully. :) It's certainly an interesting optimization. But I think that we would still need the peephole optimizer for ARM (and PPC?). X86's instructions either always set the EFLAGS register or not. A lot of ARM instructions may set CSPR, but they don't have to. And it appears that that decision needs to wait until after instruction selection...

-bw