[llvm-commits] [llvm] r60915 - in /llvm/trunk/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Target/X86/X86Instr64bit.td Target/X86/X86InstrInfo.td

[Bill Wendling]

On Fri, Dec 12, 2008 at 8:41 AM, Evan Cheng <echeng at apple.com> wrote:
> That's not what I asked. If you look at X86GenInstrInfo.inc, you will
> see:
>
>   { 41, 3,      1,      0,      "ADD32rr", 0|
> (1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,
> ImplicitList1, Barriers1, OperandInfo9 },  // Inst #41 = ADD32rr
>   { 67, 3,      1,      0,      "ADDOvf32rr", 0|
> (1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,
> ImplicitList1, Barriers1, OperandInfo9 },  // Inst #67 = ADDOvf32rr
>
> Apart from opcode number, these two instructions are identical. There
> is no reason to have a separate ADDOvf32rr instruction. You can have
> multiple patterns matching the same instruction.
>
Okay.

-bw