[llvm-commits] [llvm] r60915 - in /llvm/trunk/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Target/X86/X86Instr64bit.td Target/X86/X86InstrInfo.td

[Evan Cheng]

That's not what I asked. If you look at X86GenInstrInfo.inc, you will  
see:

   { 41, 3,      1,      0,      "ADD32rr", 0| 
(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,  
ImplicitList1, Barriers1, OperandInfo9 },  // Inst #41 = ADD32rr
   { 67, 3,      1,      0,      "ADDOvf32rr", 0| 
(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,  
ImplicitList1, Barriers1, OperandInfo9 },  // Inst #67 = ADDOvf32rr

Apart from opcode number, these two instructions are identical. There  
is no reason to have a separate ADDOvf32rr instruction. You can have  
multiple patterns matching the same instruction.

Evan

On Dec 12, 2008, at 12:18 AM, Bill Wendling wrote:

> On Dec 11, 2008, at 11:05 PM, Evan Cheng wrote:
>
>> Do we really need different instructions? How us ADD32rr different
>> from ADDvfo32er? Both implicitly define EFLAGS.
>>
> ADDOvf32rr matches on X86ISD::ADD.
>
> -bw
>
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