[llvm-commits] [llvm] r60915 - in /llvm/trunk/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Target/X86/X86Instr64bit.td Target/X86/X86InstrInfo.td

[Evan Cheng]

On Dec 12, 2008, at 9:14 AM, Bill Wendling wrote:

> On Fri, Dec 12, 2008 at 8:41 AM, Evan Cheng <echeng at apple.com> wrote:
>> That's not what I asked. If you look at X86GenInstrInfo.inc, you will
>> see:
>>
>>  { 41, 3,      1,      0,      "ADD32rr", 0|
>> (1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,
>> ImplicitList1, Barriers1, OperandInfo9 },  // Inst #41 = ADD32rr
>>  { 67, 3,      1,      0,      "ADDOvf32rr", 0|
>> (1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL,
>> ImplicitList1, Barriers1, OperandInfo9 },  // Inst #67 = ADDOvf32rr
>>
>> Apart from opcode number, these two instructions are identical. There
>> is no reason to have a separate ADDOvf32rr instruction. You can have
>> multiple patterns matching the same instruction.
>>
> Okay.

Thanks. Just to clarify, the correct thing to do is to rename  
ADDOvf32rr to ADD32rr and delete the old ADD32rr. That is, we always  
select to an X86::ADD* instruction that produces two values, with the  
second one being EFLAGS. In the *normal* case, the scheduler will see  
EFLAGS is not used and it will mark it dead.

But make sure you try it on a couple of these instructions first  
before you convert everything over. Just in case I am full of it. :-)

Evan

>
>
> -bw
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