[llvm-commits] CVS: llvm/lib/Target/IA64/IA64Bundling.cpp IA64InstrInfo.td IA64RegisterInfo.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64Bundling.cpp updated: 1.1 -> 1.2
IA64InstrInfo.td updated: 1.43 -> 1.44
IA64RegisterInfo.cpp updated: 1.12 -> 1.13
---
Log message:

some hoovering



---
Diffs of the changes:  (+13 -9)

 IA64Bundling.cpp     |    7 ++++---
 IA64InstrInfo.td     |    7 +++++--
 IA64RegisterInfo.cpp |    8 ++++----
 3 files changed, 13 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/IA64/IA64Bundling.cpp
diff -u llvm/lib/Target/IA64/IA64Bundling.cpp:1.1 llvm/lib/Target/IA64/IA64Bundling.cpp:1.2
--- llvm/lib/Target/IA64/IA64Bundling.cpp:1.1	Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64Bundling.cpp	Thu Jan 26 03:08:31 2006
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by Duraid Madina and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -56,7 +56,8 @@
 
     std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
                          // pending writes can cross basic blocks. Note that
-                         // taken branches end instruction groups.
+                         // taken branches end instruction groups. So we
+			 // only need to worry about 'fallthrough' code
   };
 } // end of anonymous namespace
 


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.43 llvm/lib/Target/IA64/IA64InstrInfo.td:1.44
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.43	Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Thu Jan 26 03:08:31 2006
@@ -501,10 +501,13 @@
 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
   "shr $dst = $src1, $imm">;
 
-def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
+def EXTRU : AForm<0x03, 0x0b,
+  (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
   "extr.u $dst = $src1, $imm1, $imm2">;
 
-def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),	  "dep.z $dst = $src1, $imm1, $imm2">;
+def DEPZ : AForm<0x03, 0x0b,
+  (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
+  "dep.z $dst = $src1, $imm1, $imm2">;
 
 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
   "($qp) cmp.eq.or $dst, p0 = $src1, $src2">;


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.12 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.13
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.12	Tue Jan 24 20:23:38 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Thu Jan 26 03:08:31 2006
@@ -168,8 +168,8 @@
   if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
     //fix up the old:
     MI.SetMachineOperandReg(i, IA64::r22);
-    MachineOperand &MO = MI.getOperand(i);
-    MO.setUse(); // mark r22 as being used (the bundler wants to know this)
+    MI.getOperand(i).setUse(); // mark r22 as being used
+                               // (the bundler wants to know this)
     //insert the new
     MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
       .addReg(BaseRegister).addSImm(Offset);
@@ -177,8 +177,8 @@
   } else { // it's big
     //fix up the old:
     MI.SetMachineOperandReg(i, IA64::r22);
-    MachineOperand &MO = MI.getOperand(i);
-    MO.setUse(); // mark r22 as being used (the bundler wants to know this)
+    MI.getOperand(i).setUse(); // mark r22 as being used
+                               // (the bundler wants to know this)
     MachineInstr* nMI;
     nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
     MBB.insert(II, nMI);