[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.14 -> 1.15
---
Log message:


fix stack corruption! Previously, 16-byte whole-FP-register stores were 
being treated as needing only 8 bytes (though they were 16 byte aligned.)

This should fix a bunch of tests - anyone have any comments, though?

  - in Target.td , SpillSize and SpillAlignment seem dead - is this what
    Size and Alignment do now?
  - in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
    DeclaredSpillAlignment seem dead.
  - there are a bunch of comments here and there that don't clearly 
    distinguish between 'size' and 'spillsize' etc. hmm.



---
Diffs of the changes:  (+7 -4)

 IA64RegisterInfo.td |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.14 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.15
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.14	Mon Jan 23 00:08:46 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Thu Jan 26 03:45:03 2006
@@ -283,10 +283,7 @@
 
 // these are the scratch (+stacked) FP registers
 
-// the 128 here is to make stf.spill/ldf.fill happy,
-// when storing full (82-bit) FP regs to stack slots
-// we need to 16-byte align
-def FP : RegisterClass<"IA64", [f64], 128, 
+def FP : RegisterClass<"IA64", [f64], 64, 
        [F6, F7, 
 	F8, F9, F10, F11, F12, F13, F14, F15, 
 	F32, F33, F34, F35, F36, F37, F38, F39, 
@@ -303,6 +300,12 @@
 	F120, F121, F122, F123, F124, F125, F126, F127,
 	F0, F1]> // these last two are hidden
   {
+// the 128s here are to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+    let Size=128;
+    let Alignment=128;
+
     let MethodProtos = [{
     iterator allocation_order_begin(MachineFunction &MF) const;
     iterator allocation_order_end(MachineFunction &MF) const;