[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCSchedule.td PPCScheduleG3.td PPCScheduleG4.td PPCScheduleG4Plus.td PPCScheduleG5.td

[Jim Laskey]

Changes in directory llvm/lib/Target/PowerPC:

PPCSchedule.td updated: 1.1 -> 1.2
PPCScheduleG3.td updated: 1.2 -> 1.3
PPCScheduleG4.td updated: 1.2 -> 1.3
PPCScheduleG4Plus.td updated: 1.2 -> 1.3
PPCScheduleG5.td updated: 1.2 -> 1.3
---
Log message:

Push processor descriptions to the top of target and add command line info.


---
Diffs of the changes:  (+40 -14)

 PPCSchedule.td       |   46 ++++++++++++++++++++++++++++++++++++----------
 PPCScheduleG3.td     |    2 +-
 PPCScheduleG4.td     |    2 +-
 PPCScheduleG4Plus.td |    2 +-
 PPCScheduleG5.td     |    2 +-
 5 files changed, 40 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCSchedule.td
diff -u llvm/lib/Target/PowerPC/PPCSchedule.td:1.1 llvm/lib/Target/PowerPC/PPCSchedule.td:1.2
--- llvm/lib/Target/PowerPC/PPCSchedule.td:1.1	Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/PowerPC/PPCSchedule.td	Wed Oct 19 08:34:52 2005
@@ -7,20 +7,11 @@
 // 
 //===----------------------------------------------------------------------===//
 
-#include "../TargetSchedule.td"
-
-//===----------------------------------------------------------------------===//
-// PowerPC chips sets supported by scheduling (Apple naming)
-//
-def G3      : Processor;
-def G4      : Processor;
-def G4Plus  : Processor;
-def G5      : Processor;
+#include "../Target.td"
 
 //===----------------------------------------------------------------------===//
 // Functional units across PowerPC chips sets
 //
-def NoUnit : FuncUnit; // Instruction not supported on chip set
 def BPU    : FuncUnit; // Branch unit
 def SLU    : FuncUnit; // Store/load unit
 def SRU    : FuncUnit; // special register unit
@@ -518,3 +509,38 @@
 //    xoris      IntGeneral
 //
 
+
+//===----------------------------------------------------------------------===//
+// PowerPC Subtarget features.
+//
+ 
+def F64Bit     : SubtargetFeature<"64bit",
+                  "Should 64 bit instructions be used">;
+def F64BitRegs : SubtargetFeature<"64bitregs",
+                  "Should 64 bit registers be used">;
+def FAltivec   : SubtargetFeature<"altivec",
+                  "Should Altivec instructions be used">;
+def FGPUL      : SubtargetFeature<"gpul",
+                  "Should GPUL instructions be used">;
+def FFSQRT     : SubtargetFeature<"fsqrt",
+                  "Should the fsqrt instruction be used">; 
+
+//===----------------------------------------------------------------------===//
+// PowerPC chips sets supported
+//
+
+def : Processor<"601", G3Itineraries, []>;
+def : Processor<"602", G3Itineraries, []>;
+def : Processor<"603", G3Itineraries, []>;
+def : Processor<"604", G3Itineraries, []>;
+def : Processor<"750", G3Itineraries, []>;
+def : Processor<"7400", G4Itineraries, [FAltivec]>;
+def : Processor<"g4", G4Itineraries, [FAltivec]>;
+def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
+def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
+def : Processor<"970", G5Itineraries,
+                  [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+def : Processor<"g5", G5Itineraries,
+                  [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
+
+


Index: llvm/lib/Target/PowerPC/PPCScheduleG3.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.2 llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.3
--- llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.2	Tue Oct 18 11:59:23 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG3.td	Wed Oct 19 08:34:52 2005
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 
-def G3Itineraries : ProcessorItineraries<G3, [
+def G3Itineraries : ProcessorItineraries<[
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,


Index: llvm/lib/Target/PowerPC/PPCScheduleG4.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.2 llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.3
--- llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.2	Tue Oct 18 11:59:23 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4.td	Wed Oct 19 08:34:52 2005
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-def G4Itineraries : ProcessorItineraries<G4, [
+def G4Itineraries : ProcessorItineraries<[
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,


Index: llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.2 llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.3
--- llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.2	Tue Oct 18 11:59:23 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td	Wed Oct 19 08:34:52 2005
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-def G4PlusItineraries : ProcessorItineraries<G4Plus, [
+def G4PlusItineraries : ProcessorItineraries<[
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
   InstrItinData<IntDivW     , [InstrStage<23, [IU2]>]>,


Index: llvm/lib/Target/PowerPC/PPCScheduleG5.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.2 llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.3
--- llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.2	Tue Oct 18 11:59:23 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG5.td	Wed Oct 19 08:34:52 2005
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-def G5Itineraries : ProcessorItineraries<G5, [
+def G5Itineraries : ProcessorItineraries<[
   InstrItinData<IntGeneral  , [InstrStage<2, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<3, [IU1, IU2]>]>,
   InstrItinData<IntDivD     , [InstrStage<68, [IU1]>]>,