[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCInstrInfo.td PPCRegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCAsmPrinter.cpp updated: 1.99 -> 1.100
PPCInstrInfo.td updated: 1.123 -> 1.124
PPCRegisterInfo.cpp updated: 1.35 -> 1.36
---
Log message:

Fix the JIT encoding of LWA, LD, STD, and STDU.


---
Diffs of the changes:  (+20 -4)

 PPCAsmPrinter.cpp   |    4 ++++
 PPCInstrInfo.td     |   11 +++++++----
 PPCRegisterInfo.cpp |    9 +++++++++
 3 files changed, 20 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.99 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.100
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.99	Sun Oct 16 00:39:50 2005
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp	Tue Oct 18 11:51:22 2005
@@ -117,6 +117,10 @@
                             MVT::ValueType VT) {
       O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
     }
+    void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo,
+                              MVT::ValueType VT) {
+      O << (short)MI->getOperand(OpNo).getImmedValue()*4;
+    }
     void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
                             MVT::ValueType VT) {
       // Branches can take an immediate operand.  This is used by the branch


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.123 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.124
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.123	Mon Oct 17 19:28:58 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Oct 18 11:51:22 2005
@@ -89,6 +89,9 @@
 def u16imm  : Operand<i32> {
   let PrintMethod = "printU16ImmOperand";
 }
+def s16immX4  : Operand<i32> {   // Multiply imm by 4 before printing.
+  let PrintMethod = "printS16X4ImmOperand";
+}
 def target : Operand<i32> {
   let PrintMethod = "printBranchOperand";
 }
@@ -282,15 +285,15 @@
 // DS-Form instructions.  Load/Store instructions available in PPC-64
 //
 let isLoad = 1 in {
-def LWA  : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def LWA  : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "lwa $rT, $DS($rA)">, isPPC64;
-def LD   : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def LD   : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "ld $rT, $DS($rA)">, isPPC64;
 }
 let isStore = 1 in {
-def STD  : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def STD  : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "std $rT, $DS($rA)">, isPPC64;
-def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "stdu $rT, $DS($rA)">, isPPC64;
 }
 


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.35 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.36
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.35	Mon Oct 17 19:28:58 2005
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Tue Oct 18 11:51:22 2005
@@ -271,6 +271,15 @@
     MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
     MI.SetMachineOperandReg(2, PPC::R0);
   } else {
+    switch (MI.getOpcode()) {
+    case PPC::LWA:
+    case PPC::LD:
+    case PPC::STD:
+    case PPC::STDU:
+      assert((Offset & 3) == 0 && "Invalid frame offset!");
+      Offset >>= 2;    // The actual encoded value has the low two bits zero.
+      break;
+    }
     MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
                               Offset);
   }