[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCSchedule.td PPCScheduleG3.td PPCScheduleG4.td PPCScheduleG4Plus.td PPCScheduleG5.td
Jim Laskey
jlaskey at apple.com
Tue Oct 18 09:23:52 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPCSchedule.td added (r1.1)
PPCScheduleG3.td added (r1.1)
PPCScheduleG4.td added (r1.1)
PPCScheduleG4Plus.td added (r1.1)
PPCScheduleG5.td added (r1.1)
---
Log message:
Checking in first round of scheduling tablegen files. Not tied in as yet.
---
Diffs of the changes: (+873 -0)
PPCSchedule.td | 520 +++++++++++++++++++++++++++++++++++++++++++++++++++
PPCScheduleG3.td | 89 ++++++++
PPCScheduleG4.td | 88 ++++++++
PPCScheduleG4Plus.td | 88 ++++++++
PPCScheduleG5.td | 88 ++++++++
5 files changed, 873 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCSchedule.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCSchedule.td:1.1
*** /dev/null Tue Oct 18 11:23:50 2005
--- llvm/lib/Target/PowerPC/PPCSchedule.td Tue Oct 18 11:23:40 2005
***************
*** 0 ****
--- 1,520 ----
+ //===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "../TargetSchedule.td"
+
+ //===----------------------------------------------------------------------===//
+ // PowerPC chips sets supported by scheduling (Apple naming)
+ //
+ def G3 : Processor;
+ def G4 : Processor;
+ def G4Plus : Processor;
+ def G5 : Processor;
+
+ //===----------------------------------------------------------------------===//
+ // Functional units across PowerPC chips sets
+ //
+ def NoUnit : FuncUnit; // Instruction not supported on chip set
+ def BPU : FuncUnit; // Branch unit
+ def SLU : FuncUnit; // Store/load unit
+ def SRU : FuncUnit; // special register unit
+ def IU1 : FuncUnit; // integer unit 1 (simple)
+ def IU2 : FuncUnit; // integer unit 2 (complex)
+ def IU3 : FuncUnit; // integer unit 3 (7450 simple)
+ def IU4 : FuncUnit; // integer unit 4 (7450 simple)
+ def FPU1 : FuncUnit; // floating point unit 1
+ def FPU2 : FuncUnit; // floating point unit 2
+ def VPU : FuncUnit; // vector permutation unit
+ def VIU1 : FuncUnit; // vector integer unit 1 (simple)
+ def VIU2 : FuncUnit; // vector integer unit 2 (complex)
+ def VFPU : FuncUnit; // vector floating point unit
+
+
+ //===----------------------------------------------------------------------===//
+ // Instruction Itinerary classes used for PowerPC
+ //
+ def IntGeneral : InstrItinClass;
+ def IntCompare : InstrItinClass;
+ def IntDivD : InstrItinClass;
+ def IntDivW : InstrItinClass;
+ def IntMFFS : InstrItinClass;
+ def IntMFVSCR : InstrItinClass;
+ def IntMTFSB0 : InstrItinClass;
+ def IntMTSRD : InstrItinClass;
+ def IntMulHD : InstrItinClass;
+ def IntMulHW : InstrItinClass;
+ def IntMulHWU : InstrItinClass;
+ def IntMulLI : InstrItinClass;
+ def IntRFID : InstrItinClass;
+ def IntRotateD : InstrItinClass;
+ def IntRotate : InstrItinClass;
+ def IntShift : InstrItinClass;
+ def IntTrapD : InstrItinClass;
+ def IntTrapW : InstrItinClass;
+ def BrB : InstrItinClass;
+ def BrCR : InstrItinClass;
+ def BrMCR : InstrItinClass;
+ def BrMCRX : InstrItinClass;
+ def LdStDCBA : InstrItinClass;
+ def LdStDCBF : InstrItinClass;
+ def LdStDCBI : InstrItinClass;
+ def LdStDCBT : InstrItinClass;
+ def LdStDSS : InstrItinClass;
+ def LdStICBI : InstrItinClass;
+ def LdStLBZUX : InstrItinClass;
+ def LdStLD : InstrItinClass;
+ def LdStLDARX : InstrItinClass;
+ def LdStLFD : InstrItinClass;
+ def LdStLFDU : InstrItinClass;
+ def LdStLHA : InstrItinClass;
+ def LdStLMW : InstrItinClass;
+ def LdStLVEBX : InstrItinClass;
+ def LdStLWA : InstrItinClass;
+ def LdStLWARX : InstrItinClass;
+ def LdStSLBIA : InstrItinClass;
+ def LdStSLBIE : InstrItinClass;
+ def LdStSTD : InstrItinClass;
+ def LdStSTDCX : InstrItinClass;
+ def LdStSTVEBX : InstrItinClass;
+ def LdStSTWCX : InstrItinClass;
+ def LdStSync : InstrItinClass;
+ def SprISYNC : InstrItinClass;
+ def SprMFSR : InstrItinClass;
+ def SprMTMSR : InstrItinClass;
+ def SprMTSR : InstrItinClass;
+ def SprTLBSYNC : InstrItinClass;
+ def SprMFCR : InstrItinClass;
+ def SprMFMSR : InstrItinClass;
+ def SprMFSPR : InstrItinClass;
+ def SprMFTB : InstrItinClass;
+ def SprMTSPR : InstrItinClass;
+ def SprMTSRIN : InstrItinClass;
+ def SprRFI : InstrItinClass;
+ def SprSC : InstrItinClass;
+ def FPGeneral : InstrItinClass;
+ def FPCompare : InstrItinClass;
+ def FPDivD : InstrItinClass;
+ def FPDivS : InstrItinClass;
+ def FPFused : InstrItinClass;
+ def FPRes : InstrItinClass;
+ def FPSqrt : InstrItinClass;
+ def VecGeneral : InstrItinClass;
+ def VecFP : InstrItinClass;
+ def VecFPCompare : InstrItinClass;
+ def VecComplex : InstrItinClass;
+ def VecPerm : InstrItinClass;
+ def VecFPRound : InstrItinClass;
+ def VecVSL : InstrItinClass;
+ def VecVSR : InstrItinClass;
+
+ //===----------------------------------------------------------------------===//
+ // Processor instruction itineraries.
+
+ #include "PPCScheduleG3.td"
+ #include "PPCScheduleG4.td"
+ #include "PPCScheduleG4Plus.td"
+ #include "PPCScheduleG5.td"
+
+ //===----------------------------------------------------------------------===//
+ // Instruction to itinerary class map - When add new opcodes to the supported
+ // set, refer to the following table to determine which itinerary class the
+ // opcode belongs.
+ //
+ // opcode itinerary class
+ // ====== ===============
+ // add IntGeneral
+ // addc IntGeneral
+ // adde IntGeneral
+ // addi IntGeneral
+ // addic IntGeneral
+ // addic. IntGeneral
+ // addis IntGeneral
+ // addme IntGeneral
+ // addze IntGeneral
+ // and IntGeneral
+ // andc IntGeneral
+ // andi. IntGeneral
+ // andis. IntGeneral
+ // b BrB
+ // bc BrB
+ // bcctr BrB
+ // bclr BrB
+ // cmp IntCompare
+ // cmpi IntCompare
+ // cmpl IntCompare
+ // cmpli IntCompare
+ // cntlzd IntRotateD
+ // cntlzw IntGeneral
+ // crand BrCR
+ // crandc BrCR
+ // creqv BrCR
+ // crnand BrCR
+ // crnor BrCR
+ // cror BrCR
+ // crorc BrCR
+ // crxor BrCR
+ // dcba LdStDCBA
+ // dcbf LdStDCBF
+ // dcbi LdStDCBI
+ // dcbst LdStDCBF
+ // dcbt LdStDCBT
+ // dcbtst LdStDCBT
+ // dcbz LdStDCBF
+ // divd IntDivD
+ // divdu IntDivD
+ // divw IntDivW
+ // divwu IntDivW
+ // dss LdStDSS
+ // dst LdStDSS
+ // dstst LdStDSS
+ // eciwx LdStDCBT
+ // ecowx LdStDCBT
+ // eieio LdStDCBT
+ // eqv IntGeneral
+ // extsb IntGeneral
+ // extsh IntGeneral
+ // extsw IntRotateD
+ // fabs FPGeneral
+ // fadd FPGeneral
+ // fadds FPGeneral
+ // fcfid FPGeneral
+ // fcmpo FPCompare
+ // fcmpu FPCompare
+ // fctid FPGeneral
+ // fctidz FPGeneral
+ // fctiw FPGeneral
+ // fctiwz FPGeneral
+ // fdiv FPDivD
+ // fdivs FPDivS
+ // fmadd FPFused
+ // fmadds FPGeneral
+ // fmr FPGeneral
+ // fmsub FPFused
+ // fmsubs FPGeneral
+ // fmul FPFused
+ // fmuls FPGeneral
+ // fnabs FPGeneral
+ // fneg FPGeneral
+ // fnmadd FPFused
+ // fnmadds FPGeneral
+ // fnmsub FPFused
+ // fnmsubs FPGeneral
+ // fres FPRes
+ // frsp FPGeneral
+ // frsqrte FPGeneral
+ // fsel FPGeneral
+ // fsqrt FPSqrt
+ // fsqrts FPSqrt
+ // fsub FPGeneral
+ // fsubs FPGeneral
+ // icbi LdStICBI
+ // isync SprISYNC
+ // lbz LdStDCBT
+ // lbzu LdStDCBT
+ // lbzux LdStLBZUX
+ // lbzx LdStDCBT
+ // ld LdStLD
+ // ldarx LdStLDARX
+ // ldu LdStLD
+ // ldux LdStLD
+ // ldx LdStLD
+ // lfd LdStLFD
+ // lfdu LdStLFDU
+ // lfdux LdStLFDU
+ // lfdx LdStLFDU
+ // lfs LdStLFDU
+ // lfsu LdStLFDU
+ // lfsux LdStLFDU
+ // lfsx LdStLFDU
+ // lha LdStLHA
+ // lhau LdStLHA
+ // lhaux LdStLHA
+ // lhax LdStLHA
+ // lhbrx LdStDCBT
+ // lhz LdStDCBT
+ // lhzu LdStDCBT
+ // lhzux LdStLBZUX
+ // lhzx LdStDCBT
+ // lmw LdStLMW
+ // lswi LdStLMW
+ // lswx LdStLMW
+ // lvebx LdStLVEBX
+ // lvehx LdStLVEBX
+ // lvewx LdStLVEBX
+ // lvsl LdStLVEBX
+ // lvsr LdStLVEBX
+ // lvx LdStLVEBX
+ // lvxl LdStLVEBX
+ // lwa LdStLWA
+ // lwarx LdStLWARX
+ // lwaux LdStLHA
+ // lwax LdStLHA
+ // lwbrx LdStDCBT
+ // lwz LdStDCBT
+ // lwzu LdStDCBT
+ // lwzux LdStLBZUX
+ // lwzx LdStDCBT
+ // mcrf BrMCR
+ // mcrfs FPGeneral
+ // mcrxr BrMCRX
+ // mfcr SprMFCR
+ // mffs IntMFFS
+ // mfmsr SprMFMSR
+ // mfspr SprMFSPR
+ // mfsr SprMFSR
+ // mfsrin SprMFSR
+ // mftb SprMFTB
+ // mfvscr IntMFVSCR
+ // mtcrf BrMCRX
+ // mtfsb0 IntMTFSB0
+ // mtfsb1 IntMTFSB0
+ // mtfsf IntMTFSB0
+ // mtfsfi IntMTFSB0
+ // mtmsr SprMTMSR
+ // mtmsrd LdStLD
+ // mtspr SprMTSPR
+ // mtsr SprMTSR
+ // mtsrd IntMTSRD
+ // mtsrdin IntMTSRD
+ // mtsrin SprMTSRIN
+ // mtvscr IntMFVSCR
+ // mulhd IntMulHD
+ // mulhdu IntMulHD
+ // mulhw IntMulHW
+ // mulhwu IntMulHWU
+ // mulld IntMulHD
+ // mulli IntMulLI
+ // mullw IntMulHW
+ // nand IntGeneral
+ // neg IntGeneral
+ // nor IntGeneral
+ // or IntGeneral
+ // orc IntGeneral
+ // ori IntGeneral
+ // oris IntGeneral
+ // rfi SprRFI
+ // rfid IntRFID
+ // rldcl IntRotateD
+ // rldcr IntRotateD
+ // rldic IntRotateD
+ // rldicl IntRotateD
+ // rldicr IntRotateD
+ // rldimi IntRotateD
+ // rlwimi IntRotate
+ // rlwinm IntGeneral
+ // rlwnm IntGeneral
+ // sc SprSC
+ // slbia LdStSLBIA
+ // slbie LdStSLBIE
+ // sld IntRotateD
+ // slw IntGeneral
+ // srad IntRotateD
+ // sradi IntRotateD
+ // sraw IntShift
+ // srawi IntShift
+ // srd IntRotateD
+ // srw IntGeneral
+ // stb LdStDCBT
+ // stbu LdStDCBT
+ // stbux LdStDCBT
+ // stbx LdStDCBT
+ // std LdStSTD
+ // stdcx. LdStSTDCX
+ // stdu LdStSTD
+ // stdux LdStSTD
+ // stdx LdStSTD
+ // stfd LdStLBZUX
+ // stfdu LdStLBZUX
+ // stfdux LdStLBZUX
+ // stfdx LdStLBZUX
+ // stfiwx LdStLBZUX
+ // stfs LdStLBZUX
+ // stfsu LdStLBZUX
+ // stfsux LdStLBZUX
+ // stfsx LdStLBZUX
+ // sth LdStDCBT
+ // sthbrx LdStDCBT
+ // sthu LdStDCBT
+ // sthux LdStDCBT
+ // sthx LdStDCBT
+ // stmw LdStLMW
+ // stswi LdStLMW
+ // stswx LdStLMW
+ // stvebx LdStSTVEBX
+ // stvehx LdStSTVEBX
+ // stvewx LdStSTVEBX
+ // stvx LdStSTVEBX
+ // stvxl LdStSTVEBX
+ // stw LdStDCBT
+ // stwbrx LdStDCBT
+ // stwcx. LdStSTWCX
+ // stwu LdStDCBT
+ // stwux LdStDCBT
+ // stwx LdStDCBT
+ // subf IntGeneral
+ // subfc IntGeneral
+ // subfe IntGeneral
+ // subfic IntGeneral
+ // subfme IntGeneral
+ // subfze IntGeneral
+ // sync LdStSync
+ // td IntTrapD
+ // tdi IntTrapD
+ // tlbia LdStSLBIA
+ // tlbie LdStDCBF
+ // tlbsync SprTLBSYNC
+ // tw IntTrapW
+ // twi IntTrapW
+ // vaddcuw VecGeneral
+ // vaddfp VecFP
+ // vaddsbs VecGeneral
+ // vaddshs VecGeneral
+ // vaddsws VecGeneral
+ // vaddubm VecGeneral
+ // vaddubs VecGeneral
+ // vadduhm VecGeneral
+ // vadduhs VecGeneral
+ // vadduwm VecGeneral
+ // vadduws VecGeneral
+ // vand VecGeneral
+ // vandc VecGeneral
+ // vavgsb VecGeneral
+ // vavgsh VecGeneral
+ // vavgsw VecGeneral
+ // vavgub VecGeneral
+ // vavguh VecGeneral
+ // vavguw VecGeneral
+ // vcfsx VecFP
+ // vcfux VecFP
+ // vcmpbfp VecFPCompare
+ // vcmpeqfp VecFPCompare
+ // vcmpequb VecGeneral
+ // vcmpequh VecGeneral
+ // vcmpequw VecGeneral
+ // vcmpgefp VecFPCompare
+ // vcmpgtfp VecFPCompare
+ // vcmpgtsb VecGeneral
+ // vcmpgtsh VecGeneral
+ // vcmpgtsw VecGeneral
+ // vcmpgtub VecGeneral
+ // vcmpgtuh VecGeneral
+ // vcmpgtuw VecGeneral
+ // vctsxs VecFP
+ // vctuxs VecFP
+ // vexptefp VecFP
+ // vlogefp VecFP
+ // vmaddfp VecFP
+ // vmaxfp VecFPCompare
+ // vmaxsb VecGeneral
+ // vmaxsh VecGeneral
+ // vmaxsw VecGeneral
+ // vmaxub VecGeneral
+ // vmaxuh VecGeneral
+ // vmaxuw VecGeneral
+ // vmhaddshs VecComplex
+ // vmhraddshs VecComplex
+ // vminfp VecFPCompare
+ // vminsb VecGeneral
+ // vminsh VecGeneral
+ // vminsw VecGeneral
+ // vminub VecGeneral
+ // vminuh VecGeneral
+ // vminuw VecGeneral
+ // vmladduhm VecComplex
+ // vmrghb VecPerm
+ // vmrghh VecPerm
+ // vmrghw VecPerm
+ // vmrglb VecPerm
+ // vmrglh VecPerm
+ // vmrglw VecPerm
+ // vmsubfp VecFP
+ // vmsummbm VecComplex
+ // vmsumshm VecComplex
+ // vmsumshs VecComplex
+ // vmsumubm VecComplex
+ // vmsumuhm VecComplex
+ // vmsumuhs VecComplex
+ // vmulesb VecComplex
+ // vmulesh VecComplex
+ // vmuleub VecComplex
+ // vmuleuh VecComplex
+ // vmulosb VecComplex
+ // vmulosh VecComplex
+ // vmuloub VecComplex
+ // vmulouh VecComplex
+ // vnor VecGeneral
+ // vor VecGeneral
+ // vperm VecPerm
+ // vpkpx VecPerm
+ // vpkshss VecPerm
+ // vpkshus VecPerm
+ // vpkswss VecPerm
+ // vpkswus VecPerm
+ // vpkuhum VecPerm
+ // vpkuhus VecPerm
+ // vpkuwum VecPerm
+ // vpkuwus VecPerm
+ // vrefp VecFPRound
+ // vrfim VecFPRound
+ // vrfin VecFPRound
+ // vrfip VecFPRound
+ // vrfiz VecFPRound
+ // vrlb VecGeneral
+ // vrlh VecGeneral
+ // vrlw VecGeneral
+ // vrsqrtefp VecFP
+ // vsel VecGeneral
+ // vsl VecVSL
+ // vslb VecGeneral
+ // vsldoi VecPerm
+ // vslh VecGeneral
+ // vslo VecPerm
+ // vslw VecGeneral
+ // vspltb VecPerm
+ // vsplth VecPerm
+ // vspltisb VecPerm
+ // vspltish VecPerm
+ // vspltisw VecPerm
+ // vspltw VecPerm
+ // vsr VecVSR
+ // vsrab VecGeneral
+ // vsrah VecGeneral
+ // vsraw VecGeneral
+ // vsrb VecGeneral
+ // vsrh VecGeneral
+ // vsro VecPerm
+ // vsrw VecGeneral
+ // vsubcuw VecGeneral
+ // vsubfp VecFP
+ // vsubsbs VecGeneral
+ // vsubshs VecGeneral
+ // vsubsws VecGeneral
+ // vsububm VecGeneral
+ // vsububs VecGeneral
+ // vsubuhm VecGeneral
+ // vsubuhs VecGeneral
+ // vsubuwm VecGeneral
+ // vsubuws VecGeneral
+ // vsum2sws VecComplex
+ // vsum4sbs VecComplex
+ // vsum4shs VecComplex
+ // vsum4ubs VecComplex
+ // vsumsws VecComplex
+ // vupkhpx VecPerm
+ // vupkhsb VecPerm
+ // vupkhsh VecPerm
+ // vupklpx VecPerm
+ // vupklsb VecPerm
+ // vupklsh VecPerm
+ // vxor VecGeneral
+ // xor IntGeneral
+ // xori IntGeneral
+ // xoris IntGeneral
+ //
+
Index: llvm/lib/Target/PowerPC/PPCScheduleG3.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.1
*** /dev/null Tue Oct 18 11:23:52 2005
--- llvm/lib/Target/PowerPC/PPCScheduleG3.td Tue Oct 18 11:23:40 2005
***************
*** 0 ****
--- 1,89 ----
+ //===- PPCScheduleG3.td - PPC G3 Scheduling Definitions ----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the itinerary class data for the G3 (750) processor.
+ //
+ //===----------------------------------------------------------------------===//
+
+
+ def G3Itineraries : ProcessorItineraries<G3, [
+ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
+ InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<IntMFVSCR , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
+ InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
+ InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
+ InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
+ InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
+ InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
+ InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
+ InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStDSS , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
+ InstrItinData<LdStLVEBX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTVEBX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
+ InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
+ InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
+ InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
+ InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
+ InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
+ InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecGeneral , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecFP , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecFPCompare, [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecComplex , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecPerm , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecFPRound , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecVSL , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecVSR , [InstrStage<0, [NoUnit]>]>
+ ]>;
Index: llvm/lib/Target/PowerPC/PPCScheduleG4.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.1
*** /dev/null Tue Oct 18 11:23:52 2005
--- llvm/lib/Target/PowerPC/PPCScheduleG4.td Tue Oct 18 11:23:40 2005
***************
*** 0 ****
--- 1,88 ----
+ //===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the itinerary class data for the G4 (7400) processor.
+ //
+ //===----------------------------------------------------------------------===//
+
+ def G4Itineraries : ProcessorItineraries<G4, [
+ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
+ InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>,
+ InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>,
+ InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
+ InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
+ InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
+ InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
+ InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
+ InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
+ InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
+ InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
+ InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>,
+ InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>,
+ InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprTLBSYNC , [InstrStage<8, [SRU]>]>,
+ InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
+ InstrItinData<SprMFTB , [InstrStage<1, [SRU]>]>,
+ InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
+ InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
+ InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
+ InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
+ InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>,
+ InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
+ InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
+ InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
+ InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
+ InstrItinData<VecComplex , [InstrStage<3, [VIU2]>]>,
+ InstrItinData<VecPerm , [InstrStage<1, [VPU]>]>,
+ InstrItinData<VecFPRound , [InstrStage<4, [VFPU]>]>,
+ InstrItinData<VecVSL , [InstrStage<1, [VIU1]>]>,
+ InstrItinData<VecVSR , [InstrStage<1, [VIU1]>]>
+ ]>;
Index: llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.1
*** /dev/null Tue Oct 18 11:23:52 2005
--- llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td Tue Oct 18 11:23:40 2005
***************
*** 0 ****
--- 1,88 ----
+ //===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the itinerary class data for the G4+ (7450) processor.
+ //
+ //===----------------------------------------------------------------------===//
+
+ def G4PlusItineraries : ProcessorItineraries<G4Plus, [
+ InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
+ InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
+ InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
+ InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
+ InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
+ InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
+ InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
+ InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
+ InstrItinData<LdStLBZUX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
+ InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
+ InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
+ InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
+ InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>,
+ InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
+ InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>,
+ InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>,
+ InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
+ InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
+ InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
+ InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
+ InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
+ InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
+ InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
+ InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>,
+ InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>,
+ InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>,
+ InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>,
+ InstrItinData<VecVSR , [InstrStage<2, [VPU]>]>
+ ]>;
Index: llvm/lib/Target/PowerPC/PPCScheduleG5.td
diff -c /dev/null llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.1
*** /dev/null Tue Oct 18 11:23:52 2005
--- llvm/lib/Target/PowerPC/PPCScheduleG5.td Tue Oct 18 11:23:40 2005
***************
*** 0 ****
--- 1,88 ----
+ //===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines the itinerary class data for the G5 (970) processor.
+ //
+ //===----------------------------------------------------------------------===//
+
+ def G5Itineraries : ProcessorItineraries<G5, [
+ InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
+ InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>,
+ InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>,
+ InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>,
+ InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>,
+ InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>,
+ InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
+ InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
+ InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
+ InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
+ InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
+ InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>,
+ InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
+ InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>,
+ InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>,
+ InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>,
+ InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
+ InstrItinData<BrCR , [InstrStage<4, [BPU]>]>,
+ InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>,
+ InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
+ InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDCBI , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
+ InstrItinData<LdStICBI , [InstrStage<0, [SLU]>]>,
+ InstrItinData<LdStLBZUX , [InstrStage<4, [SLU]>]>,
+ InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
+ InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>,
+ InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>,
+ InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>,
+ InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
+ InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>,
+ InstrItinData<LdStSLBIA , [InstrStage<0, [SLU]>]>,
+ InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>,
+ InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>,
+ InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>,
+ InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>,
+ InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
+ InstrItinData<SprISYNC , [InstrStage<0, [SLU]>]>,
+ InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
+ InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
+ InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
+ InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>,
+ InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>,
+ InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>,
+ InstrItinData<SprMTSRIN , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<SprRFI , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<SprSC , [InstrStage<1, [IU2]>]>,
+ InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
+ InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
+ InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
+ InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
+ InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>,
+ InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>,
+ InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>,
+ InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>,
+ InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>,
+ InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
+ InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>,
+ InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>,
+ InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>,
+ InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>,
+ InstrItinData<VecVSR , [InstrStage<3, [VPU]>]>
+ ]>;
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