[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCScheduleG3.td PPCScheduleG4.td PPCScheduleG4Plus.td PPCScheduleG5.td
Jim Laskey
jlaskey at apple.com
Tue Oct 18 09:59:34 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPCScheduleG3.td updated: 1.1 -> 1.2
PPCScheduleG4.td updated: 1.1 -> 1.2
PPCScheduleG4Plus.td updated: 1.1 -> 1.2
PPCScheduleG5.td updated: 1.1 -> 1.2
---
Log message:
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
---
Diffs of the changes: (+3 -61)
PPCScheduleG3.td | 26 --------------------------
PPCScheduleG4.td | 15 ---------------
PPCScheduleG4Plus.td | 12 ------------
PPCScheduleG5.td | 11 +++--------
4 files changed, 3 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCScheduleG3.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.1 llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.2
--- llvm/lib/Target/PowerPC/PPCScheduleG3.td:1.1 Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG3.td Tue Oct 18 11:59:23 2005
@@ -15,21 +15,14 @@
def G3Itineraries : ProcessorItineraries<G3, [
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
- InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
- InstrItinData<IntMFVSCR , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
- InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
- InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
- InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
@@ -39,23 +32,13 @@
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStDSS , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
- InstrItinData<LdStLVEBX , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSTVEBX , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
@@ -77,13 +60,4 @@
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
- InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecGeneral , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecFP , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecFPCompare, [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecComplex , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecPerm , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecFPRound , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecVSL , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<VecVSR , [InstrStage<0, [NoUnit]>]>
]>;
Index: llvm/lib/Target/PowerPC/PPCScheduleG4.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.1 llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.2
--- llvm/lib/Target/PowerPC/PPCScheduleG4.td:1.1 Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4.td Tue Oct 18 11:59:23 2005
@@ -14,46 +14,32 @@
def G4Itineraries : ProcessorItineraries<G4, [
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
- InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
- InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
- InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
- InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
- InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>,
- InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>,
@@ -76,7 +62,6 @@
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>,
- InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
Index: llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.1 llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.2
--- llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td:1.1 Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td Tue Oct 18 11:59:23 2005
@@ -14,35 +14,26 @@
def G4PlusItineraries : ProcessorItineraries<G4Plus, [
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
- InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
- InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
- InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
- InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
- InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
InstrItinData<LdStLBZUX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
@@ -50,8 +41,6 @@
InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
@@ -76,7 +65,6 @@
InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
- InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
Index: llvm/lib/Target/PowerPC/PPCScheduleG5.td
diff -u llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.1 llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.2
--- llvm/lib/Target/PowerPC/PPCScheduleG5.td:1.1 Tue Oct 18 11:23:40 2005
+++ llvm/lib/Target/PowerPC/PPCScheduleG5.td Tue Oct 18 11:59:23 2005
@@ -19,7 +19,6 @@
InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>,
InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
- InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
@@ -34,12 +33,10 @@
InstrItinData<BrCR , [InstrStage<4, [BPU]>]>,
InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>,
InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
- InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStDCBI , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
- InstrItinData<LdStICBI , [InstrStage<0, [SLU]>]>,
+ InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>,
InstrItinData<LdStLBZUX , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
@@ -50,14 +47,14 @@
InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>,
- InstrItinData<LdStSLBIA , [InstrStage<0, [SLU]>]>,
+ InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
- InstrItinData<SprISYNC , [InstrStage<0, [SLU]>]>,
+ InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work
InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>,
@@ -67,8 +64,6 @@
InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>,
InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>,
InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>,
- InstrItinData<SprMTSRIN , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<SprRFI , [InstrStage<0, [NoUnit]>]>,
InstrItinData<SprSC , [InstrStage<1, [IU2]>]>,
InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
More information about the llvm-commits
mailing list