[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.7 -> 1.8
---
Log message:

Split RegisterClass 'Methods' into MethodProtos and MethodBodies


---
Diffs of the changes:  (+9 -4)

 IA64RegisterInfo.td |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.8
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7	Fri Aug 19 13:50:46 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Fri Aug 19 14:13:20 2005
@@ -257,14 +257,19 @@
         r120, r121, r122, r123, r124, r125, r126, r127,
 	r0, r1, r2, r12, r13, r15, r22]> // the last 15 are special (look down)
   {
-    let Methods = [{
-
-      iterator allocation_order_begin(MachineFunction &MF) const {
+    let MethodProtos = [{
+    iterator allocation_order_begin(MachineFunction &MF) const;
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GRClass::iterator
+    GRClass::allocation_order_begin(MachineFunction &MF) const {
 	// hide registers appropriately:
 	return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
       }
 
-      iterator allocation_order_end(MachineFunction &MF) const {
+      GRClass::iterator
+      GRClass::allocation_order_end(MachineFunction &MF) const {
 	int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
 
 	// we also can't allocate registers for use as locals if they're