[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.td updated: 1.6 -> 1.7
---
Log message:

Put register classes in namespaces


---
Diffs of the changes:  (+3 -3)

 IA64RegisterInfo.td |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.6 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.7
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.6	Tue Apr 12 13:42:59 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Fri Aug 19 13:50:46 2005
@@ -233,7 +233,7 @@
 // FIXME/XXX  we also reserve r22 for calculating addresses
 // in IA64RegisterInfo.cpp
 
-def GR : RegisterClass<i64, 64, 
+def GR : RegisterClass<"IA64", i64, 64, 
        [
        
 //FIXME!: for readability, we don't want the out registers to be the first
@@ -279,7 +279,7 @@
 
 // these are the scratch (+stacked) FP registers
 // ZERO (F0) and ONE (F1) are not here
-def FP : RegisterClass<f64, 64, 
+def FP : RegisterClass<"IA64", f64, 64, 
        [F6, F7, 
 	F8, F9, F10, F11, F12, F13, F14, F15, 
 	F32, F33, F34, F35, F36, F37, F38, F39, 
@@ -296,7 +296,7 @@
 	F120, F121, F122, F123, F124, F125, F126, F127]>;
 
 // these are the predicate registers, p0 (1/TRUE) is not here
-def PR : RegisterClass<i1, 64, 
+def PR : RegisterClass<"IA64", i1, 64, 
 
 // for now, let's be wimps and only have the scratch predicate regs
  [p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> {