[llvm-commits] [parallel] CVS: llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h LiveRangeInfo.cpp Makefile PhyRegAlloc.cpp
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:03:47 PST 2004
Changes in directory llvm/lib/Target/SparcV9/RegAlloc:
AllocInfo.h updated: 1.5 -> 1.5.4.1
LiveRangeInfo.cpp updated: 1.48 -> 1.48.2.1
Makefile updated: 1.4 -> 1.4.2.1
PhyRegAlloc.cpp updated: 1.131 -> 1.131.2.1
---
Log message:
Merge from trunk
---
Diffs of the changes: (+66 -78)
Index: llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.5 llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.5.4.1
--- llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.5 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h Mon Mar 1 17:58:15 2004
@@ -79,6 +79,13 @@
}
};
+static inline std::ostream &operator << (std::ostream &OS, AllocInfo &S) {
+ OS << "(Instruction " << S.Instruction << " Operand " << S.Operand
+ << " AllocState " << S.allocStateToString () << " Placement "
+ << S.Placement << ")";
+ return OS;
+}
+
} // End llvm namespace
#endif // ALLOCINFO_H
Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.48 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.48.2.1
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.48 Sun Dec 14 07:24:15 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Mon Mar 1 17:58:15 2004
@@ -171,13 +171,13 @@
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
MInstIterator != MBB.end(); ++MInstIterator) {
- MachineInstr *MInst = *MInstIterator;
+ MachineInstr *MInst = MInstIterator;
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
//
- if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
- TM.getInstrInfo().isCall(MInst->getOpCode()))
+ if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
+ TM.getInstrInfo().isCall(MInst->getOpcode()))
CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
@@ -194,9 +194,8 @@
// set it directly in the LiveRange
if (OpI.getMachineOperand().hasAllocatedReg()) {
unsigned getClassId;
- LR->setColor(MRI.getClassRegNum(
- OpI.getMachineOperand().getAllocatedRegNum(),
- getClassId));
+ LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
+ getClassId));
}
}
@@ -212,7 +211,7 @@
if (MInst->getImplicitOp(i).hasAllocatedReg()) {
unsigned getClassId;
LR->setColor(MRI.getClassRegNum(
- MInst->getImplicitOp(i).getAllocatedRegNum(),
+ MInst->getImplicitOp(i).getReg(),
getClassId));
}
}
@@ -243,7 +242,7 @@
std::vector<MachineInstr*>::iterator It = CallRetInstrList.begin();
for( ; It != CallRetInstrList.end(); ++It) {
MachineInstr *MInst = *It;
- MachineOpCode OpCode = MInst->getOpCode();
+ MachineOpCode OpCode = MInst->getOpcode();
if ((TM.getInstrInfo()).isReturn(OpCode))
MRI.suggestReg4RetValue(MInst, *this);
@@ -330,7 +329,7 @@
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII){
- const MachineInstr *MI = *MII;
+ const MachineInstr *MI = MII;
if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
std::cerr << " *Iterating over machine instr ";
Index: llvm/lib/Target/SparcV9/RegAlloc/Makefile
diff -u llvm/lib/Target/SparcV9/RegAlloc/Makefile:1.4 llvm/lib/Target/SparcV9/RegAlloc/Makefile:1.4.2.1
--- llvm/lib/Target/SparcV9/RegAlloc/Makefile:1.4 Fri Jan 9 00:16:12 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/Makefile Mon Mar 1 17:58:15 2004
@@ -10,7 +10,7 @@
DIRS =
-LIBRARYNAME = regalloc
+LIBRARYNAME = sparcv9regalloc
BUILD_ARCHIVE = 1
Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.131 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.131.2.1
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.131 Sun Dec 14 07:24:15 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Mon Mar 1 17:58:15 2004
@@ -25,20 +25,20 @@
#include "PhyRegAlloc.h"
#include "RegAllocCommon.h"
#include "RegClass.h"
+#include "../LiveVar/FunctionLiveVarInfo.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/iOther.h"
#include "llvm/Module.h"
#include "llvm/Type.h"
#include "llvm/Analysis/LoopInfo.h"
-#include "llvm/CodeGen/FunctionLiveVarInfo.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineInstrAnnot.h"
+#include "../MachineInstrAnnot.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/InstIterator.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -233,11 +233,11 @@
// iterate over all the machine instructions in BB
for ( ; MII != MBB.end(); ++MII) {
- const MachineInstr *MInst = *MII;
+ const MachineInstr *MInst = MII;
// get the LV set after the instruction
const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
- bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
+ bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
if (isCallInst) {
// set the isCallInterference flag of each live range which extends
@@ -262,7 +262,7 @@
// another. This must be done because pseudo-instructions may be
// expanded to multiple instructions by the assembler, so all the
// operands must get distinct registers.
- if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
+ if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
addInterf4PseudoInstr(MInst);
// Also add interference for any implicit definitions in a machine
@@ -355,25 +355,13 @@
MII = MBB.insert(MII, newMI);
}
-// used by: updateMachineCode (1 time)
-inline void DeleteInstruction(MachineBasicBlock& MBB,
- MachineBasicBlock::iterator& MII) {
- MII = MBB.erase(MII);
-}
-
-// used by: updateMachineCode (1 time)
-inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
- MachineBasicBlock::iterator MII) {
- *MII = newMI;
-}
-
// used by: updateMachineCode (2 times)
inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
MachineBasicBlock& MBB,
MachineBasicBlock::iterator& MII,
const std::string& msg) {
if (!IBef.empty()) {
- MachineInstr* OrigMI = *MII;
+ MachineInstr* OrigMI = MII;
std::vector<MachineInstr *>::iterator AdIt;
for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
if (DEBUG_RA) {
@@ -391,7 +379,7 @@
MachineBasicBlock::iterator& MII,
const std::string& msg) {
if (!IAft.empty()) {
- MachineInstr* OrigMI = *MII;
+ MachineInstr* OrigMI = MII;
std::vector<MachineInstr *>::iterator AdIt;
for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
if (DEBUG_RA) {
@@ -442,14 +430,14 @@
///
void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB) {
- MachineInstr* MInst = *MII;
- unsigned Opcode = MInst->getOpCode();
+ MachineInstr* MInst = MII;
+ unsigned Opcode = MInst->getOpcode();
// Reset tmp stack positions so they can be reused for each machine instr.
MF->getInfo()->popAllTempValues();
// Mark the operands for which regs have been allocated.
- bool instrNeedsSpills = markAllocatedRegs(*MII);
+ bool instrNeedsSpills = markAllocatedRegs(MII);
#ifndef NDEBUG
// Mark that the operands have been updated. Later,
@@ -506,7 +494,7 @@
// their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
- if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
+ if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
updateInstruction(MII, MBB);
// Now, move code out of delay slots of branches and returns if needed.
@@ -523,59 +511,58 @@
//
// If the annul bit of the branch is set, neither of these is legal!
// If so, we need to handle spill differently but annulling is not yet used.
- for (MachineBasicBlock::iterator MII = MBB.begin();
- MII != MBB.end(); ++MII)
+ for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
- MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
+ TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
+ MachineBasicBlock::iterator DelaySlotMI = next(MII);
+ assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpCode()));
+ bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
+ TM.getInstrInfo().isReturn(MII->getOpcode()));
bool cond1 = (isBranch &&
- AddedInstrMap.count(MInst) &&
- AddedInstrMap[MInst].InstrnsAfter.size() > 0);
+ AddedInstrMap.count(MII) &&
+ AddedInstrMap[MII].InstrnsAfter.size() > 0);
bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
(AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
if (cond1 || cond2) {
- assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
- "FIXME: Moving an annulled delay slot instruction!");
assert(delaySlots==1 &&
"InsertBefore does not yet handle >1 delay slots!");
- InsertBefore(DelaySlotMI, MBB, MII); // MII pts back to branch
-
- // In case (1), delete it and don't replace with anything!
- // Otherwise (i.e., case (2) only) replace it with a NOP.
- if (cond1) {
- DeleteInstruction(MBB, ++MII); // MII now points to next inst.
- --MII; // reset MII for ++MII of loop
- }
- else
- SubstituteInPlace(BuildMI(TM.getInstrInfo().getNOPOpCode(),1),
- MBB, MII+1); // replace with NOP
if (DEBUG_RA) {
std::cerr << "\nRegAlloc: Moved instr. with added code: "
<< *DelaySlotMI
- << " out of delay slots of instr: " << *MInst;
+ << " out of delay slots of instr: " << *MII;
+ }
+
+ // move instruction before branch
+ MBB.insert(MII, MBB.remove(DelaySlotMI));
+
+ // On cond1 we are done (we already moved the
+ // instruction out of the delay slot). On cond2 we need
+ // to insert a nop in place of the moved instruction
+ if (cond2) {
+ MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
}
}
- else
+ else {
// For non-branch instr with delay slots (probably a call), move
// InstrAfter to the instr. in the last delay slot.
- move2DelayedInstr(*MII, *(MII+delaySlots));
- }
+ MachineBasicBlock::iterator tmp = next(MII, delaySlots);
+ move2DelayedInstr(MII, tmp);
+ }
+ }
// Finally iterate over all instructions in BB and insert before/after
for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
- MachineInstr *MInst = *MII;
+ MachineInstr *MInst = MII;
// do not process Phis
- if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
+ if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
continue;
// if there are any added instructions...
@@ -583,11 +570,11 @@
AddedInstrns &CallAI = AddedInstrMap[MInst];
#ifndef NDEBUG
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpCode()));
+ bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
+ TM.getInstrInfo().isReturn(MInst->getOpcode()));
assert((!isBranch ||
AddedInstrMap[MInst].InstrnsAfter.size() <=
- TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
+ TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
"Cannot put more than #delaySlots instrns after "
"branch or return! Need to handle temps differently.");
#endif
@@ -635,12 +622,12 @@
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
const unsigned OpNum) {
- MachineInstr *MInst = *MII;
+ MachineInstr *MInst = MII;
const BasicBlock *BB = MBB.getBasicBlock();
- assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
+ assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
- assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
+ assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
"Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
@@ -658,8 +645,8 @@
// include all live variables before that branch or return -- we don't want to
// trample those! Verify that the set is included in the LV set before MInst.
if (MII != MBB.begin()) {
- MachineInstr *PredMI = *(MII-1);
- if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
+ MachineBasicBlock::iterator PredMI = prior(MII);
+ if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
"live-var set of each delay slot instruction!");
@@ -745,7 +732,7 @@
std::vector<MachineInstr*> &instrnsAfter,
MachineInstr *CallMI,
const BasicBlock *BB) {
- assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
+ assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
// hash set to record which registers were saved/restored
hash_set<unsigned> PushedRegSet;
@@ -1030,12 +1017,11 @@
// explicit and implicit operands are set.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).hasAllocatedReg())
- markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
+ markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
if (MI->getImplicitOp(i).hasAllocatedReg())
- markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
- RegType,MRI);
+ markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
// Add all of the scratch registers that are used to save values across the
// instruction (e.g., for saving state register values).
@@ -1201,12 +1187,8 @@
std::cerr << "FnAllocState:\n";
for (unsigned i = 0; i < state.size (); ++i) {
AllocInfo &S = state[i];
- if (Insn == S.Instruction) {
- std::cerr << " (Instruction " << S.Instruction
- << ", Operand " << S.Operand
- << ", AllocState " << S.allocStateToString ()
- << ", Placement " << S.Placement << ")\n";
- }
+ if (Insn == S.Instruction)
+ std::cerr << " " << S << "\n";
}
std::cerr << "----------\n";
++Insn;
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