[llvm-commits] [parallel] CVS: llvm/lib/Target/SparcV8/InstSelectSimple.cpp Makefile README.txt SparcV8.h SparcV8.td SparcV8CodeEmitter.cpp SparcV8InstrInfo.cpp SparcV8InstrInfo.h SparcV8InstrInfo.td SparcV8InstrInfo_F2.td SparcV8InstrInfo_F3.td SparcV8JITInfo.h SparcV8RegisterInfo.cpp SparcV8RegisterInfo.h SparcV8RegisterInfo.td SparcV8TargetMachine.cpp SparcV8TargetMachine.h
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:03:38 PST 2004
Changes in directory llvm/lib/Target/SparcV8:
InstSelectSimple.cpp added (r1.1.2.1)
Makefile added (r1.2.2.1)
README.txt added (r1.1.2.1)
SparcV8.h added (r1.2.2.1)
SparcV8.td added (r1.3.2.1)
SparcV8CodeEmitter.cpp added (r1.1.2.1)
SparcV8InstrInfo.cpp added (r1.3.2.1)
SparcV8InstrInfo.h added (r1.2.2.1)
SparcV8InstrInfo.td added (r1.1.2.1)
SparcV8InstrInfo_F2.td added (r1.1.2.1)
SparcV8InstrInfo_F3.td added (r1.1.2.1)
SparcV8JITInfo.h added (r1.1.2.1)
SparcV8RegisterInfo.cpp added (r1.3.2.1)
SparcV8RegisterInfo.h added (r1.1.2.1)
SparcV8RegisterInfo.td added (r1.3.2.1)
SparcV8TargetMachine.cpp added (r1.4.2.1)
SparcV8TargetMachine.h added (r1.2.2.1)
---
Log message:
Merge from trunk
---
Diffs of the changes: (+946 -0)
Index: llvm/lib/Target/SparcV8/InstSelectSimple.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/InstSelectSimple.cpp:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/InstSelectSimple.cpp Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,152 ----
+ //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines a simple peephole instruction selector for the V8 target
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8.h"
+ #include "llvm/Instructions.h"
+ #include "llvm/IntrinsicLowering.h"
+ #include "llvm/Pass.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Support/GetElementPtrTypeIterator.h"
+ #include "llvm/Support/InstVisitor.h"
+ #include "llvm/Support/CFG.h"
+ using namespace llvm;
+
+ namespace {
+ struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
+ TargetMachine &TM;
+ MachineFunction *F; // The function we are compiling into
+ MachineBasicBlock *BB; // The current MBB we are compiling
+
+ std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
+
+ // MBBMap - Mapping between LLVM BB -> Machine BB
+ std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
+
+ V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
+
+ /// runOnFunction - Top level implementation of instruction selection for
+ /// the entire function.
+ ///
+ bool runOnFunction(Function &Fn);
+
+ virtual const char *getPassName() const {
+ return "SparcV8 Simple Instruction Selection";
+ }
+
+ /// visitBasicBlock - This method is called when we are visiting a new basic
+ /// block. This simply creates a new MachineBasicBlock to emit code into
+ /// and adds it to the current MachineFunction. Subsequent visit* for
+ /// instructions will be invoked for all instructions in the basic block.
+ ///
+ void visitBasicBlock(BasicBlock &LLVM_BB) {
+ BB = MBBMap[&LLVM_BB];
+ }
+
+ void visitReturnInst(ReturnInst &RI);
+
+ void visitInstruction(Instruction &I) {
+ std::cerr << "Unhandled instruction: " << I;
+ abort();
+ }
+
+ /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
+ /// function, lowering any calls to unknown intrinsic functions into the
+ /// equivalent LLVM code.
+ void LowerUnknownIntrinsicFunctionCalls(Function &F);
+
+
+ void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
+
+ };
+ }
+
+ FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
+ return new V8ISel(TM);
+ }
+
+
+ bool V8ISel::runOnFunction(Function &Fn) {
+ // First pass over the function, lower any unknown intrinsic functions
+ // with the IntrinsicLowering class.
+ LowerUnknownIntrinsicFunctionCalls(Fn);
+
+ F = &MachineFunction::construct(&Fn, TM);
+
+ // Create all of the machine basic blocks for the function...
+ for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
+
+ BB = &F->front();
+
+ // Set up a frame object for the return address. This is used by the
+ // llvm.returnaddress & llvm.frameaddress intrinisics.
+ //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
+
+ // Copy incoming arguments off of the stack and out of fixed registers.
+ //LoadArgumentsToVirtualRegs(Fn);
+
+ // Instruction select everything except PHI nodes
+ visit(Fn);
+
+ // Select the PHI nodes
+ //SelectPHINodes();
+
+ RegMap.clear();
+ MBBMap.clear();
+ F = 0;
+ // We always build a machine code representation for the function
+ return true;
+ }
+
+
+ void V8ISel::visitReturnInst(ReturnInst &I) {
+ if (I.getNumOperands() == 0) {
+ // Just emit a 'ret' instruction
+ BuildMI(BB, V8::JMPLi, 2, V8::G0).addZImm(8).addReg(V8::I7);
+ return;
+ }
+ visitInstruction(I);
+ }
+
+
+ /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
+ /// function, lowering any calls to unknown intrinsic functions into the
+ /// equivalent LLVM code.
+ void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
+ for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
+ for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
+ if (CallInst *CI = dyn_cast<CallInst>(I++))
+ if (Function *F = CI->getCalledFunction())
+ switch (F->getIntrinsicID()) {
+ case Intrinsic::not_intrinsic: break;
+ default:
+ // All other intrinsic calls we must lower.
+ Instruction *Before = CI->getPrev();
+ TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
+ if (Before) { // Move iterator to instruction after call
+ I = Before; ++I;
+ } else {
+ I = BB->begin();
+ }
+ }
+ }
+
+
+ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
+ unsigned TmpReg1, TmpReg2;
+ switch (ID) {
+ default: assert(0 && "Intrinsic not supported!");
+ }
+ }
Index: llvm/lib/Target/SparcV8/Makefile
diff -c /dev/null llvm/lib/Target/SparcV8/Makefile:1.2.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/Makefile Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,46 ----
+ ##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
+ #
+ # The LLVM Compiler Infrastructure
+ #
+ # This file was developed by the LLVM research group and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ #
+ ##===----------------------------------------------------------------------===##
+ LEVEL = ../../..
+ LIBRARYNAME = sparcv8
+ include $(LEVEL)/Makefile.common
+
+ TDFILES := $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
+ TDFILE := $(SourceDir)/SparcV8.td
+
+ # Make sure that tblgen is run, first thing.
+ $(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
+ SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
+ SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
+
+ SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td register names with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-enums -o $@
+
+ SparcV8GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td register information header with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc-header -o $@
+
+ SparcV8GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td register information implementation with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc -o $@
+
+ SparcV8GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td instruction names with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-enums -o $@
+
+ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td instruction information with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
+
+ SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
+ @echo "Building SparcV8.td instruction selector with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
+
+ clean::
+ $(VERB) rm -f *.inc
Index: llvm/lib/Target/SparcV8/README.txt
diff -c /dev/null llvm/lib/Target/SparcV8/README.txt:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/README.txt Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,9 ----
+
+ SparcV8 backend skeleton
+ ------------------------
+
+ This directory will house a 32-bit SPARC V8 backend employing a expander-based
+ instruction selector. Watch this space for more news coming soon!
+
+ $Date: 2004/03/01 23:58:14 $
+
Index: llvm/lib/Target/SparcV8/SparcV8.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8.h:1.2.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8.h Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,40 ----
+ //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the entry points for global functions defined in the LLVM
+ // SparcV8 back-end.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef TARGET_SPARCV8_H
+ #define TARGET_SPARCV8_H
+
+ #include <iosfwd>
+
+ namespace llvm {
+
+ class FunctionPass;
+ class TargetMachine;
+
+ FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
+ // FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
+ // TargetMachine &TM);
+
+ } // end namespace llvm;
+
+ // Defines symbolic names for SparcV8 registers. This defines a mapping from
+ // register name to register number.
+ //
+ #include "SparcV8GenRegisterNames.inc"
+
+ // Defines symbolic names for the SparcV8 instructions.
+ //
+ #include "SparcV8GenInstrNames.inc"
+
+ #endif
Index: llvm/lib/Target/SparcV8/SparcV8.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8.td:1.3.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8.td Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,38 ----
+ //===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ // Get the target-independent interfaces which we are implementing...
+ //
+ include "../Target.td"
+
+ //===----------------------------------------------------------------------===//
+ // Register File Description
+ //===----------------------------------------------------------------------===//
+
+ include "SparcV8RegisterInfo.td"
+ include "SparcV8InstrInfo.td"
+
+ def SparcV8InstrInfo : InstrInfo {
+ let PHIInst = PHI;
+ }
+
+ def SparcV8 : Target {
+ // Pointers are 32-bits in size.
+ let PointerType = i32;
+
+ // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+ // calls:
+ let CalleeSavedRegisters = [];
+
+ // Pull in Instruction Info:
+ let InstructionSet = SparcV8InstrInfo;
+ }
Index: llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,43 ----
+ //===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8TargetMachine.h"
+
+ namespace llvm {
+
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
+ /// machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions. This method should returns true if machine code emission is
+ /// not supported.
+ ///
+ bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE) {
+ return true;
+ // It should go something like this:
+ // PM.add(new Emitter(MCE)); // Machine code emitter pass for SparcV8
+ // Delete machine code for this function after emitting it:
+ // PM.add(createMachineCodeDeleter());
+ }
+
+ void *SparcV8JITInfo::getJITStubForFunction(Function *F,
+ MachineCodeEmitter &MCE) {
+ assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
+ return 0;
+ }
+
+ void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
+ assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
+ }
+
+ } // end llvm namespace
+
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.3.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,22 ----
+ //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8InstrInfo.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "SparcV8GenInstrInfo.inc"
+ using namespace llvm;
+
+ SparcV8InstrInfo::SparcV8InstrInfo()
+ : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
+ }
+
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.2.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.h Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,36 ----
+ //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef SPARCV8INSTRUCTIONINFO_H
+ #define SPARCV8INSTRUCTIONINFO_H
+
+ #include "llvm/Target/TargetInstrInfo.h"
+ #include "SparcV8RegisterInfo.h"
+
+ namespace llvm {
+
+ class SparcV8InstrInfo : public TargetInstrInfo {
+ const SparcV8RegisterInfo RI;
+ public:
+ SparcV8InstrInfo();
+
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
+ /// such, whenever a client has an instance of instruction info, it should
+ /// always be able to get register info as well (through this method).
+ ///
+ virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ };
+
+ }
+
+ #endif
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,68 ----
+ //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file describes the SparcV8 instructions in TableGen format.
+ //
+ //===----------------------------------------------------------------------===//
+
+ //===----------------------------------------------------------------------===//
+ // Instruction format superclass
+ //===----------------------------------------------------------------------===//
+
+ class InstV8 : Instruction { // SparcV8 instruction baseline
+ field bits<32> Inst;
+
+ let Namespace = "V8";
+
+ bits<2> op;
+ let Inst{31-30} = op; // Top two bits are the 'op' field
+
+ // Bit attributes specific to SparcV8 instructions
+ bit isPasi = 0; // Does this instruction affect an alternate addr space?
+ bit isPrivileged = 0; // Is this a privileged instruction?
+ }
+
+ include "SparcV8InstrInfo_F2.td"
+ include "SparcV8InstrInfo_F3.td"
+
+ //===----------------------------------------------------------------------===//
+ // Instructions
+ //===----------------------------------------------------------------------===//
+
+ // Pseudo instructions.
+ def PHI : InstV8 {
+ let Name = "PHI";
+ }
+ def ADJCALLSTACKDOWN : InstV8 {
+ let Name = "ADJCALLSTACKDOWN";
+ }
+ def ADJCALLSTACKUP : InstV8 {
+ let Name = "ADJCALLSTACKUP";
+ }
+
+ // Section B.20: SAVE and RESTORE - p117
+ def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
+ def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
+ def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
+ def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
+
+ // Section B.24: Call and Link - p125
+ // This is the only Format 1 instruction
+ def CALL : InstV8 {
+ bits<30> disp;
+
+ let op = 1;
+ let Inst{29-0} = disp;
+ let Name = "call";
+ }
+
+ // Section B.25: Jump and Link - p126
+ def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
+ def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
+
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo_F2.td Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,44 ----
+ //===- SparcV8Instrs_F2.td - Format 2 instructions: SparcV8 Target --------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Format #2 instruction classes in the SparcV8
+ //
+ //===----------------------------------------------------------------------===//
+
+ class F2 : InstV8 { // Format 2 instructions
+ bits<3> op2;
+ bits<22> imm22;
+ let op = 0; // op = 0
+ let Inst{24-22} = op2;
+ let Inst{21-0} = imm22;
+ }
+
+ // Specific F2 classes: SparcV8 manual, page 44
+ //
+ class F2_1<bits<3> op2Val, string name> : F2 {
+ bits<5> rd;
+ bits<22> imm;
+
+ let op2 = op2Val;
+ let Name = name;
+
+ let Inst{29-25} = rd;
+ }
+
+ class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
+ bits<4> cond;
+ bit annul = 0; // currently unused
+
+ let cond = condVal;
+ let op2 = op2Val;
+ let Name = name;
+
+ let Inst{29} = annul;
+ let Inst{28-25} = cond;
+ }
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo_F3.td Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,62 ----
+ //===- SparcV8Instrs_F3.td - Format 3 Instructions: SparcV8 Target --------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Format #3 instruction classes in the SparcV8
+ //
+ //===----------------------------------------------------------------------===//
+
+ class F3 : InstV8 {
+ bits<5> rd;
+ bits<6> op3;
+ bits<5> rs1;
+ let op{1} = 1; // Op = 2 or 3
+ let Inst{29-25} = rd;
+ let Inst{24-19} = op3;
+ let Inst{18-14} = rs1;
+ }
+
+ // Specific F3 classes: SparcV8 manual, page 44
+ //
+ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
+ bits<8> asi;
+ bits<5> rs2;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13} = 0; // i field = 0
+ let Inst{12-5} = asi; // address space identifier
+ let Inst{4-0} = rs2;
+ }
+
+ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
+ bits<13> simm13;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13} = 1; // i field = 1
+ let Inst{12-0} = simm13;
+ }
+
+ /*
+ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
+ : F3_rs1rs2 {
+ bits<5> rs2;
+
+ let op = opVal;
+ let op3 = op3val;
+ let Name = name;
+
+ let Inst{13-5} = opfVal;
+ let Inst{4-0} = rs2;
+ }
+ */
\ No newline at end of file
Index: llvm/lib/Target/SparcV8/SparcV8JITInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8JITInfo.h:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8JITInfo.h Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,49 ----
+ //===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the TargetJITInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef SPARCV8JITINFO_H
+ #define SPARCV8JITINFO_H
+
+ #include "llvm/Target/TargetJITInfo.h"
+
+ namespace llvm {
+ class TargetMachine;
+ class IntrinsicLowering;
+
+ class SparcV8JITInfo : public TargetJITInfo {
+ TargetMachine &TM;
+ public:
+ SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
+
+ /// addPassesToJITCompile - Add passes to the specified pass manager to
+ /// implement a fast dynamic compiler for this target. Return true if this
+ /// is not supported for this target.
+ ///
+ virtual void addPassesToJITCompile(FunctionPassManager &PM);
+
+ /// replaceMachineCodeForFunction - Make it so that calling the function
+ /// whose machine code is at OLD turns into a call to NEW, perhaps by
+ /// overwriting OLD with a branch to NEW. This is used for self-modifying
+ /// code.
+ ///
+ virtual void replaceMachineCodeForFunction(void *Old, void *New);
+
+ /// getJITStubForFunction - Create or return a stub for the specified
+ /// function. This stub acts just like the specified function, except that
+ /// it allows the "address" of the function to be taken without having to
+ /// generate code for it.
+ virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
+ };
+ }
+
+ #endif
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.3.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,107 ----
+ //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8.h"
+ #include "SparcV8RegisterInfo.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/Type.h"
+ #include "Support/STLExtras.h"
+ using namespace llvm;
+
+ SparcV8RegisterInfo::SparcV8RegisterInfo()
+ : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
+ V8::ADJCALLSTACKUP) {}
+
+ int SparcV8RegisterInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIdx,
+ const TargetRegisterClass *RC) const
+ {
+ abort();
+ return -1;
+ }
+
+ int SparcV8RegisterInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const
+ {
+ abort();
+ return -1;
+ }
+
+ int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const {
+ abort();
+ return -1;
+ }
+
+ void SparcV8RegisterInfo::
+ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
+ abort();
+ }
+
+ void
+ SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
+ MachineBasicBlock::iterator II) const {
+ abort();
+ }
+
+ void SparcV8RegisterInfo::
+ processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
+
+ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
+ MachineBasicBlock &MBB = MF.front();
+
+ // Eventually this should emit the correct save instruction based on the
+ // number of bytes in the frame. For now we just hardcode it.
+ BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
+ }
+
+ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
+ MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ assert(MBBI->getOpcode() == V8::JMPLi &&
+ "Can only put epilog before return instruction!");
+ BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
+ }
+
+
+ #include "SparcV8GenRegisterInfo.inc"
+
+ const TargetRegisterClass*
+ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
+ switch (Ty->getPrimitiveID()) {
+ case Type::FloatTyID:
+ case Type::DoubleTyID:
+ assert(0 && "Floating point registers not supported yet!");
+ case Type::LongTyID:
+ case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
+ default: assert(0 && "Invalid type to getClass!");
+ case Type::BoolTyID:
+ case Type::SByteTyID:
+ case Type::UByteTyID:
+ case Type::ShortTyID:
+ case Type::UShortTyID:
+ case Type::IntTyID:
+ case Type::UIntTyID:
+ case Type::PointerTyID: return &IntRegsInstance;
+ }
+ }
+
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,58 ----
+ //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the SparcV8 implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef SPARCV8REGISTERINFO_H
+ #define SPARCV8REGISTERINFO_H
+
+ #include "llvm/Target/MRegisterInfo.h"
+ #include "SparcV8GenRegisterInfo.h.inc"
+
+ namespace llvm {
+
+ class Type;
+
+ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
+ SparcV8RegisterInfo();
+ const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+
+ /// Code Generation virtual methods...
+ int storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ int loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const;
+
+ void eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const;
+
+ void eliminateFrameIndex(MachineFunction &MF,
+ MachineBasicBlock::iterator II) const;
+
+ void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
+
+ void emitPrologue(MachineFunction &MF) const;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ };
+
+ } // end namespace llvm
+
+ #endif
Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td:1.3.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,45 ----
+ //===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // Declarations that describe the SparcV8 register file
+ //
+ //===----------------------------------------------------------------------===//
+
+ // Ri - 32-bit integer registers
+ class Ri<bits<5> num> : Register {
+ field bits<5> Num = num; // Numbers are identified with a 5 bit ID
+ }
+
+ let Namespace = "V8" in {
+ def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
+ def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
+ def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
+ def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
+ def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
+ def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
+ def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
+ def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
+
+ // Standard register aliases.
+ def SP : Ri<14>; def FP : Ri<30>;
+
+ // Floating-point registers?
+ // ...
+ }
+
+
+ // For fun, specify a register class.
+ //
+ // FIXME: the register order should be defined in terms of the preferred
+ // allocation order...
+ //
+ def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O6, O7,
+ L0, L1, L2, L3, L4, L5, L6, L7,
+ I0, I1, I2, I3, I4, I5, I6, I7]>;
Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.4.2.1
*** /dev/null Mon Mar 1 17:58:29 2004
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,67 ----
+ //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "SparcV8TargetMachine.h"
+ #include "SparcV8.h"
+ #include "llvm/Module.h"
+ #include "llvm/PassManager.h"
+ #include "llvm/Target/TargetMachineImpls.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/Passes.h"
+ using namespace llvm;
+
+ // allocateSparcV8TargetMachine - Allocate and return a subclass of
+ // TargetMachine that implements the SparcV8 backend.
+ //
+ TargetMachine *llvm::allocateSparcV8TargetMachine(const Module &M,
+ IntrinsicLowering *IL) {
+ return new SparcV8TargetMachine(M, IL);
+ }
+
+ /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
+ ///
+ SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
+ IntrinsicLowering *IL)
+ : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
+ FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
+ }
+
+ /// addPassesToEmitAssembly - Add passes to the specified pass manager
+ /// to implement a static compiler for this target.
+ ///
+ bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
+ std::ostream &Out) {
+ PM.add(createSparcV8SimpleInstructionSelector(*this));
+
+ // Print machine instructions as they are created.
+ PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
+ PM.add(createRegisterAllocator());
+ PM.add(createPrologEpilogCodeInserter());
+ // <insert assembly code output passes here>
+
+ // This is not a correct asm writer by any means, but at least we see what we
+ // are producing.
+ PM.add(createMachineFunctionPrinterPass(&Out));
+
+ PM.add(createMachineCodeDeleter());
+ return false;
+ }
+
+ /// addPassesToJITCompile - Add passes to the specified pass manager to
+ /// implement a fast dynamic compiler for this target.
+ ///
+ void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+ // <insert instruction selector passes here>
+ PM.add(createRegisterAllocator());
+ PM.add(createPrologEpilogCodeInserter());
+ }
Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8TargetMachine.h:1.2.2.1
*** /dev/null Mon Mar 1 17:58:29 2004
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.h Mon Mar 1 17:58:14 2004
***************
*** 0 ****
--- 1,60 ----
+ //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file declares the SparcV8 specific subclass of TargetMachine.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef SPARCV8TARGETMACHINE_H
+ #define SPARCV8TARGETMACHINE_H
+
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/TargetFrameInfo.h"
+ #include "llvm/PassManager.h"
+ #include "SparcV8InstrInfo.h"
+ #include "SparcV8JITInfo.h"
+
+ namespace llvm {
+
+ class IntrinsicLowering;
+
+ class SparcV8TargetMachine : public TargetMachine {
+ SparcV8InstrInfo InstrInfo;
+ TargetFrameInfo FrameInfo;
+ SparcV8JITInfo JITInfo;
+ public:
+ SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
+
+ virtual const SparcV8InstrInfo &getInstrInfo() const { return InstrInfo; }
+ virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
+ virtual const MRegisterInfo *getRegisterInfo() const {
+ return &InstrInfo.getRegisterInfo();
+ }
+ virtual TargetJITInfo *getJITInfo() {
+ return &JITInfo;
+ }
+
+ virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
+ virtual const TargetRegInfo &getRegInfo() const { abort(); }
+
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+ /// get machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions. This method should returns true if machine code emission is
+ /// not supported.
+ ///
+ virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE);
+
+ virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+ };
+
+ } // end namespace llvm
+
+ #endif
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