[llvm-commits] [parallel] CVS: llvm/lib/Target/PowerPC/Makefile PowerPC.h PowerPC.td PowerPCCodeEmitter.cpp PowerPCInstrInfo.cpp PowerPCInstrInfo.h PowerPCInstrs.td PowerPCJITInfo.h PowerPCReg.td PowerPCRegisterInfo.cpp PowerPCRegisterInfo.h PowerPCTargetMachine.cpp PowerPCTargetMachine.h README.txt
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:03:55 PST 2004
Changes in directory llvm/lib/Target/PowerPC:
Makefile added (r1.1.2.1)
PowerPC.h added (r1.2.2.1)
PowerPC.td added (r1.1.2.1)
PowerPCCodeEmitter.cpp added (r1.1.2.1)
PowerPCInstrInfo.cpp added (r1.3.2.1)
PowerPCInstrInfo.h added (r1.2.2.1)
PowerPCInstrs.td added (r1.1.2.1)
PowerPCJITInfo.h added (r1.1.2.1)
PowerPCReg.td added (r1.1.2.1)
PowerPCRegisterInfo.cpp added (r1.4.2.1)
PowerPCRegisterInfo.h added (r1.4.2.1)
PowerPCTargetMachine.cpp added (r1.7.2.1)
PowerPCTargetMachine.h added (r1.4.2.1)
README.txt added (r1.2.2.1)
---
Log message:
Merge from trunk
---
Diffs of the changes: (+717 -0)
Index: llvm/lib/Target/PowerPC/Makefile
diff -c /dev/null llvm/lib/Target/PowerPC/Makefile:1.1.2.1
*** /dev/null Mon Mar 1 17:58:27 2004
--- llvm/lib/Target/PowerPC/Makefile Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,55 ----
+ ##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===##
+ #
+ # The LLVM Compiler Infrastructure
+ #
+ # This file was developed by the LLVM research group and is distributed under
+ # the University of Illinois Open Source License. See LICENSE.TXT for details.
+ #
+ ##===----------------------------------------------------------------------===##
+ LEVEL = ../../..
+ LIBRARYNAME = powerpc
+ include $(LEVEL)/Makefile.common
+
+ # Make sure that tblgen is run, first thing.
+ $(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \
+ PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \
+ PowerPCGenInstrInfo.inc PowerPCGenInstrSelector.inc
+
+ PowerPCGenRegisterNames.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCReg.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td register names with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
+
+ PowerPCGenRegisterInfo.h.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCReg.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td register information header with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
+
+ PowerPCGenRegisterInfo.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCReg.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td register information implementation with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
+
+ PowerPCGenInstrNames.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCInstrs.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td instruction names with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
+
+ PowerPCGenInstrInfo.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCInstrs.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td instruction information with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
+
+ PowerPCGenInstrSelector.inc:: $(SourceDir)/PowerPC.td \
+ $(SourceDir)/PowerPCInstrs.td \
+ $(SourceDir)/../Target.td $(TBLGEN)
+ @echo "Building PowerPC.td instruction selector with tblgen"
+ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
+
+ clean::
+ $(VERB) rm -f *.inc
Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPC.h:1.2.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPC.h Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,42 ----
+ //===-- PowerPC.h - Top-level interface for PowerPC representation -*- C++ -*-//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the entry points for global functions defined in the LLVM
+ // PowerPC back-end.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef TARGET_POWERPC_H
+ #define TARGET_POWERPC_H
+
+ #include <iosfwd>
+
+ namespace llvm {
+
+ class FunctionPass;
+ class TargetMachine;
+
+ // Here is where you would define factory methods for powerpc-specific
+ // passes. For example:
+ // FunctionPass *createPowerPCSimpleInstructionSelector (TargetMachine &TM);
+ // FunctionPass *createPowerPCCodePrinterPass(std::ostream &OS,
+ // TargetMachine &TM);
+
+ } // end namespace llvm;
+
+ // Defines symbolic names for PowerPC registers. This defines a mapping from
+ // register name to register number.
+ //
+ #include "PowerPCGenRegisterNames.inc"
+
+ // Defines symbolic names for the PowerPC instructions.
+ //
+ #include "PowerPCGenInstrNames.inc"
+
+ #endif
Index: llvm/lib/Target/PowerPC/PowerPC.td
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPC.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPC.td Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,41 ----
+ //===- PowerPC.td - Describe the PowerPC Target Machine ---------*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ // Get the target-independent interfaces which we are implementing...
+ //
+ include "../Target.td"
+
+ //===----------------------------------------------------------------------===//
+ // Register File Description
+ //===----------------------------------------------------------------------===//
+
+ include "PowerPCReg.td"
+ include "PowerPCInstrs.td"
+
+ def PowerPCInstrInfo : InstrInfo {
+ let PHIInst = PHI;
+ }
+
+ def PowerPC : Target {
+ // Pointers are 32-bits in size.
+ let PointerType = i32;
+
+ // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+ // calls:
+ let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+ R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+ F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+ F30, F31, CR2, CR3, CR4];
+
+ // Pull in Instruction Info:
+ let InstructionSet = PowerPCInstrInfo;
+ }
Index: llvm/lib/Target/PowerPC/PowerPCCodeEmitter.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCCodeEmitter.cpp:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCCodeEmitter.cpp Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,43 ----
+ //===-- PowerPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----*- C++ -*-=//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "PowerPCTargetMachine.h"
+
+ namespace llvm {
+
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
+ /// machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions. This method should returns true if machine code emission is
+ /// not supported.
+ ///
+ bool PowerPCTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE) {
+ return true;
+ // It should go something like this:
+ // PM.add(new Emitter(MCE)); // Machine code emitter pass for PowerPC
+ // Delete machine code for this function after emitting it:
+ // PM.add(createMachineCodeDeleter());
+ }
+
+ void *PowerPCJITInfo::getJITStubForFunction(Function *F,
+ MachineCodeEmitter &MCE) {
+ assert (0 && "PowerPCJITInfo::getJITStubForFunction not implemented");
+ return 0;
+ }
+
+ void PowerPCJITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
+ assert (0 && "PowerPCJITInfo::replaceMachineCodeForFunction not implemented");
+ }
+
+ } // end llvm namespace
+
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp:1.3.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,21 ----
+ //===- PowerPCInstrInfo.cpp - PowerPC Instruction Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "PowerPCInstrInfo.h"
+ #include "llvm/CodeGen/MachineInstrBuilder.h"
+ #include "PowerPCGenInstrInfo.inc"
+ using namespace llvm;
+
+ PowerPCInstrInfo::PowerPCInstrInfo()
+ : TargetInstrInfo(PowerPCInsts, sizeof(PowerPCInsts)/sizeof(PowerPCInsts[0])){
+ }
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.2.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.h Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,36 ----
+ //===- PowerPCInstrInfo.h - PowerPC Instruction Information -----*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the TargetInstrInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPCINSTRUCTIONINFO_H
+ #define POWERPCINSTRUCTIONINFO_H
+
+ #include "llvm/Target/TargetInstrInfo.h"
+ #include "PowerPCRegisterInfo.h"
+
+ namespace llvm {
+
+ class PowerPCInstrInfo : public TargetInstrInfo {
+ const PowerPCRegisterInfo RI;
+ public:
+ PowerPCInstrInfo();
+
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
+ /// such, whenever a client has an instance of instruction info, it should
+ /// always be able to get register info as well (through this method).
+ ///
+ virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
+ };
+
+ }
+
+ #endif
Index: llvm/lib/Target/PowerPC/PowerPCInstrs.td
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCInstrs.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCInstrs.td Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,46 ----
+ //===- PowerPCInstrInfo.td - Describe the PowerPC Instruction Set -*- C++ -*-=//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ class Format<bits<4> val> {
+ bits<4> Value = val;
+ }
+
+ // All of the PowerPC instruction formats, plus a pseudo-instruction format:
+ def Pseudo : Format<0>;
+ def IForm : Format<1>;
+ def BForm : Format<2>;
+ def SCForm : Format<3>;
+ def DForm : Format<4>;
+ def XForm : Format<5>;
+ def XLForm : Format<6>;
+ def XFXForm : Format<7>;
+ def XFLForm : Format<8>;
+ def XOForm : Format<9>;
+ def AForm : Format<10>;
+ def MForm : Format<11>;
+
+ class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
+ let Namespace = "PowerPC";
+
+ let Name = nm;
+ bits<6> Opcode = opcd;
+ Format Form = f;
+ bits<4> FormBits = Form.Value;
+ }
+
+ // Pseudo-instructions:
+ def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
+ def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
+ def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
+ def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
+
+
Index: llvm/lib/Target/PowerPC/PowerPCJITInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCJITInfo.h:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCJITInfo.h Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,49 ----
+ //===- PowerPCJITInfo.h - PowerPC impl. of the JIT interface ----*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the TargetJITInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPCJITINFO_H
+ #define POWERPCJITINFO_H
+
+ #include "llvm/Target/TargetJITInfo.h"
+
+ namespace llvm {
+ class TargetMachine;
+ class IntrinsicLowering;
+
+ class PowerPCJITInfo : public TargetJITInfo {
+ TargetMachine &TM;
+ public:
+ PowerPCJITInfo(TargetMachine &tm) : TM(tm) {}
+
+ /// addPassesToJITCompile - Add passes to the specified pass manager to
+ /// implement a fast dynamic compiler for this target. Return true if this
+ /// is not supported for this target.
+ ///
+ virtual void addPassesToJITCompile(FunctionPassManager &PM);
+
+ /// replaceMachineCodeForFunction - Make it so that calling the function
+ /// whose machine code is at OLD turns into a call to NEW, perhaps by
+ /// overwriting OLD with a branch to NEW. This is used for self-modifying
+ /// code.
+ ///
+ virtual void replaceMachineCodeForFunction(void *Old, void *New);
+
+ /// getJITStubForFunction - Create or return a stub for the specified
+ /// function. This stub acts just like the specified function, except that
+ /// it allows the "address" of the function to be taken without having to
+ /// generate code for it.
+ virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
+ };
+ }
+
+ #endif
Index: llvm/lib/Target/PowerPC/PowerPCReg.td
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCReg.td:1.1.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCReg.td Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,82 ----
+ //===- PowerPCReg.td - Describe the PowerPC Register File -------*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ class PPCReg : Register {
+ let Namespace = "PowerPC";
+ }
+
+ // We identify all our registers with a 5-bit ID, for consistency's sake.
+
+ // GPR - One of the 32 32-bit general-purpose registers
+ class GPR<bits<5> num> : PPCReg {
+ field bits<5> Num = num;
+ }
+
+ // SPR - One of the 32-bit special-purpose registers
+ class SPR<bits<5> num> : PPCReg {
+ field bits<5> Num = num;
+ }
+
+ // FPR - One of the 32 64-bit floating-point registers
+ class FPR<bits<5> num> : PPCReg {
+ field bits<5> Num = num;
+ }
+
+ // CR - One of the 8 4-bit condition registers
+ class CR<bits<5> num> : PPCReg {
+ field bits<5> Num = num;
+ }
+
+ // General-purpose registers
+ def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
+ def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
+ def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
+ def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
+ def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
+ def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
+ def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
+ def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
+
+ // Floating-point registers
+ def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
+ def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
+ def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
+ def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
+ def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
+ def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
+ def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
+ def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
+
+ // Condition registers
+ def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
+ def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
+
+ // Floating-point status and control register
+ def FPSCR : SPR<0>;
+ // fiXed-point Exception Register? :-)
+ def XER : SPR<1>;
+ // Link register
+ def LR : SPR<2>;
+ // Count register
+ def CTR : SPR<3>;
+ // These are the "time base" registers which are read-only in user mode.
+ def TBL : SPR<4>;
+ def TBU : SPR<5>;
+
+ /// Register classes: one for floats and another for non-floats.
+ def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
+ R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
+ R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
+ def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
+ F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+ F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp:1.4.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,99 ----
+ //===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "PowerPC.h"
+ #include "PowerPCRegisterInfo.h"
+ #include "llvm/Type.h"
+ using namespace llvm;
+
+ PowerPCRegisterInfo::PowerPCRegisterInfo()
+ : PowerPCGenRegisterInfo(PowerPC::ADJCALLSTACKDOWN,
+ PowerPC::ADJCALLSTACKUP) {}
+
+ int PowerPCRegisterInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIdx,
+ const TargetRegisterClass *RC) const
+ {
+ abort();
+ return -1;
+ }
+
+ int PowerPCRegisterInfo::loadRegFromStackSlot(
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const
+ {
+ abort();
+ return -1;
+ }
+
+ int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const {
+ abort();
+ return -1;
+ }
+
+ void PowerPCRegisterInfo::
+ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const {
+ abort();
+ }
+
+ void
+ PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
+ MachineBasicBlock::iterator II) const {
+ abort();
+ }
+
+ void PowerPCRegisterInfo::processFunctionBeforeFrameFinalized(
+ MachineFunction &MF) const {
+ abort();
+ }
+
+ void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
+ abort();
+ }
+
+ void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {
+ abort();
+ }
+
+
+ #include "PowerPCGenRegisterInfo.inc"
+
+ const TargetRegisterClass*
+ PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
+ switch (Ty->getPrimitiveID()) {
+ case Type::LongTyID:
+ case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
+ default: assert(0 && "Invalid type to getClass!");
+ case Type::BoolTyID:
+ case Type::SByteTyID:
+ case Type::UByteTyID:
+ case Type::ShortTyID:
+ case Type::UShortTyID:
+ case Type::IntTyID:
+ case Type::UIntTyID:
+ case Type::PointerTyID: return &GPRCInstance;
+
+ case Type::FloatTyID:
+ case Type::DoubleTyID: return &FPRCInstance;
+ }
+ }
+
Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.4.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,58 ----
+ //===- PowerPCRegisterInfo.h - PowerPC Register Information Impl -*- C++ -*-==//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the PowerPC implementation of the MRegisterInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPCREGISTERINFO_H
+ #define POWERPCREGISTERINFO_H
+
+ #include "llvm/Target/MRegisterInfo.h"
+ #include "PowerPCGenRegisterInfo.h.inc"
+
+ namespace llvm {
+
+ class Type;
+
+ struct PowerPCRegisterInfo : public PowerPCGenRegisterInfo {
+ PowerPCRegisterInfo();
+ const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
+
+ /// Code Generation virtual methods...
+ int storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ int loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *RC) const;
+
+ void eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const;
+
+ void eliminateFrameIndex(MachineFunction &MF,
+ MachineBasicBlock::iterator II) const;
+
+ void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
+
+ void emitPrologue(MachineFunction &MF) const;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ };
+
+ } // end namespace llvm
+
+ #endif
Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.7.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,59 ----
+ //===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ //
+ //===----------------------------------------------------------------------===//
+
+ #include "PowerPCTargetMachine.h"
+ #include "PowerPC.h"
+ #include "llvm/Module.h"
+ #include "llvm/PassManager.h"
+ #include "llvm/Target/TargetMachineImpls.h"
+ #include "llvm/CodeGen/MachineFunction.h"
+ #include "llvm/CodeGen/Passes.h"
+ using namespace llvm;
+
+ // allocatePowerPCTargetMachine - Allocate and return a subclass of
+ // TargetMachine that implements the PowerPC backend.
+ //
+ TargetMachine *llvm::allocatePowerPCTargetMachine(const Module &M,
+ IntrinsicLowering *IL) {
+ return new PowerPCTargetMachine(M, IL);
+ }
+
+ /// PowerPCTargetMachine ctor - Create an ILP32 architecture model
+ ///
+ PowerPCTargetMachine::PowerPCTargetMachine(const Module &M,
+ IntrinsicLowering *IL)
+ : TargetMachine("PowerPC", IL, true, 4, 4, 4, 4, 4),
+ FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
+ }
+
+ /// addPassesToEmitAssembly - Add passes to the specified pass manager
+ /// to implement a static compiler for this target.
+ ///
+ bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
+ std::ostream &Out) {
+ // <insert instruction selector passes here>
+ PM.add(createRegisterAllocator());
+ PM.add(createPrologEpilogCodeInserter());
+ // <insert assembly code output passes here>
+ PM.add(createMachineCodeDeleter());
+ return true; // change to `return false' when this actually works.
+ }
+
+ /// addPassesToJITCompile - Add passes to the specified pass manager to
+ /// implement a fast dynamic compiler for this target.
+ ///
+ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+ // <insert instruction selector passes here>
+ PM.add(createRegisterAllocator());
+ PM.add(createPrologEpilogCodeInserter());
+ }
+
Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.h
diff -c /dev/null llvm/lib/Target/PowerPC/PowerPCTargetMachine.h:1.4.2.1
*** /dev/null Mon Mar 1 17:58:28 2004
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.h Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,60 ----
+ //===-- PowerPCTargetMachine.h - Define TargetMachine for PowerPC -*- C++ -*-=//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the LLVM research group and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file declares the PowerPC specific subclass of TargetMachine.
+ //
+ //===----------------------------------------------------------------------===//
+
+ #ifndef POWERPCTARGETMACHINE_H
+ #define POWERPCTARGETMACHINE_H
+
+ #include "llvm/Target/TargetMachine.h"
+ #include "llvm/Target/TargetFrameInfo.h"
+ #include "llvm/PassManager.h"
+ #include "PowerPCInstrInfo.h"
+ #include "PowerPCJITInfo.h"
+
+ namespace llvm {
+
+ class IntrinsicLowering;
+
+ class PowerPCTargetMachine : public TargetMachine {
+ PowerPCInstrInfo InstrInfo;
+ TargetFrameInfo FrameInfo;
+ PowerPCJITInfo JITInfo;
+ public:
+ PowerPCTargetMachine(const Module &M, IntrinsicLowering *IL);
+
+ virtual const PowerPCInstrInfo &getInstrInfo() const { return InstrInfo; }
+ virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
+ virtual const MRegisterInfo *getRegisterInfo() const {
+ return &InstrInfo.getRegisterInfo();
+ }
+ virtual TargetJITInfo *getJITInfo() {
+ return &JITInfo;
+ }
+
+ virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
+ virtual const TargetRegInfo &getRegInfo() const { abort(); }
+
+ /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
+ /// get machine code emitted. This uses a MachineCodeEmitter object to handle
+ /// actually outputting the machine code and resolving things like the address
+ /// of functions. This method should returns true if machine code emission is
+ /// not supported.
+ ///
+ virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE);
+
+ virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+ };
+
+ } // end namespace llvm
+
+ #endif
Index: llvm/lib/Target/PowerPC/README.txt
diff -c /dev/null llvm/lib/Target/PowerPC/README.txt:1.2.2.1
*** /dev/null Mon Mar 1 17:58:29 2004
--- llvm/lib/Target/PowerPC/README.txt Mon Mar 1 17:58:13 2004
***************
*** 0 ****
--- 1,26 ----
+
+ PowerPC backend skeleton
+ ------------------------
+
+ Someday we'd like to have a PowerPC backend. Unfortunately, this
+ is not yet that day.
+
+ This directory contains mainly stubs and placeholders; there is no
+ binary machine code emitter, no assembly writer, and no instruction
+ selector here. Most of the functions in these files call abort()
+ or fail assertions on purpose, just to reinforce the fact that they
+ don't work.
+
+ If you want to use LLVM on the PowerPC *today*, use the C Backend
+ (llc -march=c). It generates C code that you can compile with the
+ native GCC compiler and run. A distant second choice would be the
+ Interpreter (lli --force-interpreter=true).
+
+ A few things *are* really here, including:
+ * PowerPC register file definition in TableGen format
+ * PowerPC definitions of TargetMachine and other target-specific classes
+
+ "Patches," as they say, "are accepted."
+
+ $Date: 2004/03/01 23:58:13 $
+
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