[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/construct.cpp

[Anand Shukla]

Changes in directory llvm/lib/Reoptimizer/BinInterface:

construct.cpp updated: 1.4 -> 1.5

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/construct.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.4 llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.5
--- llvm/lib/Reoptimizer/BinInterface/construct.cpp:1.4	Sat May 31 17:07:40 2003
+++ llvm/lib/Reoptimizer/BinInterface/construct.cpp	Wed Jun  4 04:40:38 2003
@@ -395,12 +395,15 @@
   for (int v=0;v<32;v++)
     map[v] = 0;
   
-  create_exits_liveouts(regmaps);
-  
   // Update gen fields for instructions (can't be done
   // in last pass due to insertion of PHI's)
   process_markgen(SECTION_PROLOG, map);
   process_markgen(SECTION_TRACE , map);
+
+  //for each PHI, insert a new SSA instruction
+  process_phis();
+
+  create_exits_liveouts(regmaps);
   
   // For each epilog
   for (unsigned int s=SECTION_TRACE+1;s<sections.size();s++){
@@ -418,6 +421,7 @@
 	continue;
       
       instruction * instr = itable[ssaid];
+      /*
       if (instr->flags & IF_PHI){
 	// if any of the PHI parameters are marked live out,
 	// the phi node itself becomes liveout.
@@ -433,9 +437,50 @@
 	// this one is liveout.  Let's do the insertion
 	shuffles->push_back(shufflepair(i,ssaid));
       }
+      */
+      
+      shuffles->push_back(shufflepair(i,ssaid));
     }
     // place the shuffler node
     allocnodeshuffles(s, shuffles);
   }
 }
 
+void BinInterface::process_phis(){
+  for (unsigned int i = begin(SECTION_TRACE); i!=end(SECTION_TRACE); ){
+    instruction *instr = itable[i];
+    
+    if(instr->flags & IF_PHI){
+      vector<unsigned> *vec = new vector<unsigned>();
+      for (unsigned int s = 0; s< instr->phi.params->size(); s++){
+	unsigned int j = (*instr->phi.params)[s];
+	instruction *phiArgInstr = itable[j];
+	if(phiArgInstr->flags & IF_NODELIVEIN){
+	  vec->push_back(j);
+	  continue;
+	}
+	
+	assert(phiArgInstr->flags & IF_W_RD && 
+	       "Phi instr must write into a reg");
+
+	//create a new move instruction, and insert it AFTER j
+	unsigned int movInstr = MK_MOV_R_R(instr->instr, 0);
+	unsigned int newCid = newaluOnlyRs2(movInstr, j);
+	itable[newCid]->flags |= IF_W_RD; //it writes into a destination
+	move(newCid, j);
+	
+	//if(itable[j]->flags & IF_LIVEOUT){
+	//itable[newCid]->flags |= IF_LIVEOUT;
+	//itable[j]->flags &= ~(IF_LIVEOUT);
+	//}
+
+	vec->push_back(newCid);
+      }
+      
+      delete instr->phi.params;
+      instr->phi.params = vec;
+    }
+
+    i = instr->next;
+  }
+}