[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/select.cpp

[Anand Shukla]

Changes in directory llvm/lib/Reoptimizer/BinInterface:

select.cpp updated: 1.5 -> 1.6

---
Log message:

Fixed some bugs with register pressure and spills, and added some more ALU instruction constructors

---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/select.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/select.cpp:1.5 llvm/lib/Reoptimizer/BinInterface/select.cpp:1.6
--- llvm/lib/Reoptimizer/BinInterface/select.cpp:1.5	Sat May 31 21:36:20 2003
+++ llvm/lib/Reoptimizer/BinInterface/select.cpp	Wed Jun  4 04:40:48 2003
@@ -26,6 +26,8 @@
 //
 //*****************************************************************************
 
+#define FOR_DEBUG
+
 void BinInterface::select(regalloc & regs)
 {
    regs.touched_regs = 0;    // mask containing all the touched registers
@@ -264,36 +266,43 @@
 	 
 	 //if this is last use, free up the machine reg
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
 	   
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
        
        if (flags & IF_R_RS2){
 	 int vid = ssa_to_vreg[instr->alu.genrs2];
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
 
        if (flags & IF_R_RD){
 	 int vid = ssa_to_vreg[instr->alu.genrd];
 	 if (vregs[vid].lastuse == i && vregs[vid].mreg != 0){
-	   freeregs.freereg(vregs[vid].mreg);
-	   if (VREG_ISREG(vregs[vid].mreg))
+	   //freeregs.freereg(vregs[vid].mreg);
+	   if (VREG_ISREG(vregs[vid].mreg)){
+	     freeregs.freereg(vregs[vid].mreg);
 	     hwregs[vregs[vid].mreg] = 0;
+	   }
 	 }
        }
        
        if ((flags & IF_W_RD) || ((flags & IF_RS1_RS2_DEFINED) && 
 				 !(flags & IF_BR))){
-	 assert((!(flags & IF_RS1_RS2_DEFINED) || 
-		 (flags & IF_RS1_RS2_DEFINED) && !(flags & IF_LIVEOUT)) && 
-		"liveout for new instructions not implemented");
+	 // assert((!(flags & IF_RS1_RS2_DEFINED) || 
+	 // (flags & IF_RS1_RS2_DEFINED) && !(flags & IF_LIVEOUT)) && 
+	 //"liveout for new instructions not implemented");
 	 
 	 bool skipIteration = false;
 	 //make sure this instruction is not in pinned
@@ -378,8 +387,6 @@
 	   hwregs[dreg]   = id;
 	   vregs[id].mreg = dreg;
 	 }
-	 
-	 vregs[id].mreg = dreg;
        }
      }
    }