[llvm-commits] CVS: llvm/lib/Target/X86/FloatingPoint.cpp InstSelectSimple.cpp MachineCodeEmitter.cpp Printer.cpp X86InstrInfo.cpp X86InstrInfo.def X86InstrInfo.h
Chris Lattner
lattner at cs.uiuc.edu
Tue Jan 14 16:00:03 PST 2003
Changes in directory llvm/lib/Target/X86:
FloatingPoint.cpp updated: 1.1 -> 1.2
InstSelectSimple.cpp updated: 1.81 -> 1.82
MachineCodeEmitter.cpp updated: 1.18 -> 1.19
Printer.cpp updated: 1.33 -> 1.34
X86InstrInfo.cpp updated: 1.11 -> 1.12
X86InstrInfo.def updated: 1.48 -> 1.49
X86InstrInfo.h updated: 1.20 -> 1.21
---
Log message:
Rename MachineInstrInfo -> TargetInstrInfo
---
Diffs of the changes:
Index: llvm/lib/Target/X86/FloatingPoint.cpp
diff -u llvm/lib/Target/X86/FloatingPoint.cpp:1.1 llvm/lib/Target/X86/FloatingPoint.cpp:1.2
--- llvm/lib/Target/X86/FloatingPoint.cpp:1.1 Sun Jan 12 19:01:59 2003
+++ llvm/lib/Target/X86/FloatingPoint.cpp Tue Jan 14 15:59:16 2003
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>
Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.81 llvm/lib/Target/X86/InstSelectSimple.cpp:1.82
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.81 Sun Jan 12 18:32:26 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp Tue Jan 14 15:59:16 2003
@@ -437,7 +437,7 @@
/// the current one.
///
void ISel::SelectPHINodes() {
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@@ -468,7 +468,7 @@
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
- MII.isTerminatorInstr((*(PI-1))->getOpcode()))
+ TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);
Index: llvm/lib/Target/X86/MachineCodeEmitter.cpp
diff -u llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.18 llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.19
--- llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.18 Sun Jan 12 18:33:59 2003
+++ llvm/lib/Target/X86/MachineCodeEmitter.cpp Tue Jan 14 15:59:16 2003
@@ -220,7 +220,7 @@
}
}
-unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@@ -236,7 +236,7 @@
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
- const MachineInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
Index: llvm/lib/Target/X86/Printer.cpp
diff -u llvm/lib/Target/X86/Printer.cpp:1.33 llvm/lib/Target/X86/Printer.cpp:1.34
--- llvm/lib/Target/X86/Printer.cpp:1.33 Sun Jan 12 18:35:03 2003
+++ llvm/lib/Target/X86/Printer.cpp Tue Jan 14 15:59:16 2003
@@ -59,7 +59,7 @@
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@@ -80,7 +80,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
@@ -136,7 +136,7 @@
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@@ -204,7 +204,7 @@
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.11 llvm/lib/Target/X86/X86InstrInfo.cpp:1.12
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.11 Tue Dec 17 19:05:54 2002
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Tue Jan 14 15:59:16 2003
@@ -1,6 +1,6 @@
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
@@ -17,7 +17,7 @@
// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
// descriptors
//
-static const MachineInstrDescriptor X86Insts[] = {
+static const TargetInstrDescriptor X86Insts[] = {
#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS) \
{ NAME, \
-1, /* Always vararg */ \
@@ -35,7 +35,7 @@
};
X86InstrInfo::X86InstrInfo()
- : MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+ : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
}
Index: llvm/lib/Target/X86/X86InstrInfo.def
diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.48 llvm/lib/Target/X86/X86InstrInfo.def:1.49
--- llvm/lib/Target/X86/X86InstrInfo.def:1.48 Sun Jan 12 18:48:46 2003
+++ llvm/lib/Target/X86/X86InstrInfo.def Tue Jan 14 15:59:16 2003
@@ -51,7 +51,7 @@
// #2: Opcode name, as used by the gnu assembler
// #3: The base opcode for the instruction
// #4: Instruction Flags - This should be a field or'd together that contains
-// constants from the MachineInstrInfo.h file.
+// constants from the TargetInstrInfo.h file.
// #5: Target Specific Flags - Another bitfield containing X86 specific flags
// that we are interested in for each instruction. These should be flags
// defined in X86InstrInfo.h in the X86II namespace.
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.20 llvm/lib/Target/X86/X86InstrInfo.h:1.21
--- llvm/lib/Target/X86/X86InstrInfo.h:1.20 Sun Jan 12 18:49:24 2003
+++ llvm/lib/Target/X86/X86InstrInfo.h Tue Jan 14 15:59:16 2003
@@ -1,13 +1,13 @@
//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef X86INSTRUCTIONINFO_H
#define X86INSTRUCTIONINFO_H
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
/// X86II - This namespace holds all of the target specific flags that
@@ -137,12 +137,12 @@
};
}
-class X86InstrInfo : public MachineInstrInfo {
+class X86InstrInfo : public TargetInstrInfo {
const X86RegisterInfo RI;
public:
X86InstrInfo();
- /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
More information about the llvm-commits
mailing list