[llvm-bugs] [Bug 132667] [RISC-V] Is RISC-V vector LMUL being considered as a factor for instruction scheduling in MachineScheduler implementation?

LLVM Bugs via llvm-bugs llvm-bugs at lists.llvm.org
Sun Mar 23 21:21:55 PDT 2025

Previous message: [llvm-bugs] [Bug 132666] [AVX-512] Consider that summing every odd element of an array can be done without gathers/perms
Next message: [llvm-bugs] [Bug 132668] Non-constant tuple_size in structured binding is accepted
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20250324/d8151cce/attachment.html>

Previous message: [llvm-bugs] [Bug 132666] [AVX-512] Consider that summing every odd element of an array can be done without gathers/perms
Next message: [llvm-bugs] [Bug 132668] Non-constant tuple_size in structured binding is accepted
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-bugs mailing list