<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/132667>132667</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V] Is RISC-V vector LMUL being considered as a factor for instruction scheduling in MachineScheduler implementation?
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          zhongchengyong
      </td>
    </tr>
</table>

<pre>
    The RVV instruction occupy the function unit more than one cycle when LMUL > 1, but as far as I know from the current `MachineScheduler.cpp` implementation, it seems that the LMUL is NOT considered as a factor for instruction scheduling.  
Thanks!
</pre>
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