[llvm-bugs] [Bug 173787] [InstCombine] `foldBitCeil` miscompiles non-power-of-two integer widths

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Sun Dec 28 08:30:47 PST 2025

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Previous message: [llvm-bugs] [Bug 173785] [AMDGPU] Assertion `calculateDivergence(N) == N->isDivergent() && "Divergence bit inconsistency detected"' failed.
Next message: [llvm-bugs] [Bug 173793] [InstCombine] Vector `fshl` retains invalid `range` after demanded-bits simplification
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