[llvm-bugs] [Bug 52160] New: RISC-V Vector extension intrinsic function will generate illegal RVV instruction

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=52160

            Bug ID: 52160
           Summary: RISC-V Vector extension intrinsic function will
                    generate illegal RVV instruction
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: RISC-V
          Assignee: unassignedbugs at nondot.org
          Reporter: piyou at andestech.com
                CC: asb at lowrisc.org, llvm-bugs at lists.llvm.org

The following C source code using RVV intrinsic function will generate illegal
instruction.

#include <riscv_vector.h>

void foo() {
    vfloat32m1_t v1;
    vfloat32m1_t v2;
    float dst[100];
    v2 = vrgather_vx_f32m1(v1, 0, 0);
    vse32_v_f32m1(dst, v2, 0);
}


The corresponding assembly: 

foo:                                    # @foo
        addi    sp, sp, -416
        vsetivli        zero, 0, e32, m1, ta, mu
        vrgather.vi     v25, v25, 0
        addi    a0, sp, 16
        vse32.v v25, (a0)
        addi    sp, sp, 416
        ret


test on 
clang version 14.0.0 (https://github.com/llvm/llvm-project.git
b5e8348bf2ded134e45dab879a13d26f5b9c5815)
with option 
-march=rv64gcv0p10 -O2 -menable-experimental-extensions


According to RVV spec[1], vrgather instruction the destination vector register
group cannot overlap with the source vector register groups.

Is it a backend bug or is it a reasonable result due to using uninitialized
variables?

[1]
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#164-vector-register-gather-instructions

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20211013/ab30175c/attachment.html>