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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - RISC-V Vector extension intrinsic function will generate illegal RVV instruction"
href="https://bugs.llvm.org/show_bug.cgi?id=52160">52160</a>
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<th>Summary</th>
<td>RISC-V Vector extension intrinsic function will generate illegal RVV instruction
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: RISC-V
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>piyou@andestech.com
</td>
</tr>
<tr>
<th>CC</th>
<td>asb@lowrisc.org, llvm-bugs@lists.llvm.org
</td>
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<p>
<div>
<pre>The following C source code using RVV intrinsic function will generate illegal
instruction.
#include <riscv_vector.h>
void foo() {
vfloat32m1_t v1;
vfloat32m1_t v2;
float dst[100];
v2 = vrgather_vx_f32m1(v1, 0, 0);
vse32_v_f32m1(dst, v2, 0);
}
The corresponding assembly:
foo: # @foo
addi sp, sp, -416
vsetivli zero, 0, e32, m1, ta, mu
vrgather.vi v25, v25, 0
addi a0, sp, 16
vse32.v v25, (a0)
addi sp, sp, 416
ret
test on
clang version 14.0.0 (<a href="https://github.com/llvm/llvm-project.git">https://github.com/llvm/llvm-project.git</a>
b5e8348bf2ded134e45dab879a13d26f5b9c5815)
with option
-march=rv64gcv0p10 -O2 -menable-experimental-extensions
According to RVV spec[1], vrgather instruction the destination vector register
group cannot overlap with the source vector register groups.
Is it a backend bug or is it a reasonable result due to using uninitialized
variables?
[1]
<a href="https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#164-vector-register-gather-instructions">https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#164-vector-register-gather-instructions</a></pre>
</div>
</p>
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