[llvm-bugs] [Bug 50483] New: [MCA] In-order pipeline doesn't track memory load/store dependencies.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=50483

            Bug ID: 50483
           Summary: [MCA] In-order pipeline doesn't track memory
                    load/store dependencies.
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llvm-mca
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: andrea.dibiagio at gmail.com, llvm-bugs at lists.llvm.org,
                    matthew.davis at sony.com

The in-order pipeline is not tracking loads and stores, and therefore, it is
completely ignoring load/store dependencies.

Example:

> cat foo.s

```
str x1, [x4]
ldr x2, [x4]
```


> llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --timeline --iterations=5 --noalias=false


```
Instruction Info:
[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)

[1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 1      4     1.00           *            str   x1, [x4]
 1      3     1.00    *                   ldr   x2, [x4]


Timeline view:
Index     012345678

[0,0]     DeeeE.  .   str x1, [x4]
[0,1]     .DeeE.  .   ldr x2, [x4]
[1,0]     .DeeeE  .   str x1, [x4]
[1,1]     . DeeE  .   ldr x2, [x4]
[2,0]     . DeeeE .   str x1, [x4]
[2,1]     .  DeeE .   ldr x2, [x4]
[3,0]     .  DeeeE.   str x1, [x4]
[3,1]     .   DeeE.   ldr x2, [x4]
[4,0]     .   DeeeE   str x1, [x4]
[4,1]     .    DeeE   ldr x2, [x4]
```

When flag --noalias=false is specified, younger loads are not allowed to pass
older stores. Flag --noalias=false literally means "assume that younger loads
may-alias older stores".

However, the timeline clearly shows how loads are not waiting for the store
completion.

==

For reference: this is what happens if the same code is simulated on a
cortex-a57 (which, however, is an out-of-order processor).

```
Timeline view:
                    0123456789
Index     0123456789          01234567

[0,0]     DeER .    .    .    .    . .   str    x1, [x4]
[0,1]     D=eeeeER  .    .    .    . .   ldr    x2, [x4]
[1,0]     D=====eER .    .    .    . .   str    x1, [x4]
[1,1]     .D=====eeeeER  .    .    . .   ldr    x2, [x4]
[2,0]     .D=========eER .    .    . .   str    x1, [x4]
[2,1]     .D==========eeeeER  .    . .   ldr    x2, [x4]
[3,0]     . D=============eER .    . .   str    x1, [x4]
[3,1]     . D==============eeeeER  . .   ldr    x2, [x4]
[4,0]     . D==================eER . .   str    x1, [x4]
[4,1]     .  D==================eeeeER   ldr    x2, [x4]
```

The out-of-order simulation pipeline uses an LSU to simulate load/store
accesses and track memory dependencies between operations.

When flag -noalias=false is specified, loads are correctly delayed until older
stores have fully executed.

Note that by default, flag -noalias is always set to true, so, by default,
loads don't need to wait for older stores because the assumption is that they
won't alias.

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