[llvm-bugs] [Bug 50353] New: [MCA] Additional pre-scheduler Queue modelling

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=50353

            Bug ID: 50353
           Summary: [MCA] Additional pre-scheduler Queue modelling
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: llvm-mca
          Assignee: unassignedbugs at nondot.org
          Reporter: lebedev.ri at gmail.com
                CC: andrea.dibiagio at gmail.com, llvm-bugs at lists.llvm.org,
                    matthew.davis at sony.com

AMD SOG 19h, 2.11 Floating-Point Unit
Macro ops can be dispatched to the 64 entry Non Scheduling Queue (NSQ) even if
floating-point scheduler is full to allow loads and stores to be accelerated.

As far as i'm aware this can not be modelled currently.

This is somewhat related to the #50350.

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