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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [MCA] Additional pre-scheduler Queue modelling"
href="https://bugs.llvm.org/show_bug.cgi?id=50353">50353</a>
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<th>Summary</th>
<td>[MCA] Additional pre-scheduler Queue modelling
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>llvm-mca
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>lebedev.ri@gmail.com
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
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<p>
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<pre>AMD SOG 19h, 2.11 Floating-Point Unit
Macro ops can be dispatched to the 64 entry Non Scheduling Queue (NSQ) even if
floating-point scheduler is full to allow loads and stores to be accelerated.
As far as i'm aware this can not be modelled currently.
This is somewhat related to the #50350.</pre>
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