[llvm-bugs] [Bug 49484] New: Wrong encoding for vector ld/st whole register instructions

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=49484

            Bug ID: 49484
           Summary: Wrong encoding for vector ld/st whole register
                    instructions
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: RISC-V
          Assignee: unassignedbugs at nondot.org
          Reporter: arcbbb at gmail.com
                CC: asb at lowrisc.org, llvm-bugs at lists.llvm.org

The following assembly:

    vs8r.v v24, (a0)

Generates a wrong encoding [0x27,0x0c,0x85,0x02].
which should be [0x27,0x0c,0x85,0xe2]

Similarly, vs1r/vs2r/vs4r & vl1r/vl2r/vl4r/vl8r go the same.

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