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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Wrong encoding for vector ld/st whole register instructions"
href="https://bugs.llvm.org/show_bug.cgi?id=49484">49484</a>
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<th>Summary</th>
<td>Wrong encoding for vector ld/st whole register instructions
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: RISC-V
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>arcbbb@gmail.com
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<th>CC</th>
<td>asb@lowrisc.org, llvm-bugs@lists.llvm.org
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<p>
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<pre>The following assembly:
vs8r.v v24, (a0)
Generates a wrong encoding [0x27,0x0c,0x85,0x02].
which should be [0x27,0x0c,0x85,0xe2]
Similarly, vs1r/vs2r/vs4r & vl1r/vl2r/vl4r/vl8r go the same.</pre>
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