[llvm-bugs] [Bug 50813] New: [RISCV] wrong vector register alloc in vector instruction

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=50813

            Bug ID: 50813
           Summary: [RISCV] wrong vector register alloc  in vector
                    instruction
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: tangxingxin1008 at gmail.com
                CC: htmldeveloper at gmail.com, llvm-bugs at lists.llvm.org

There is a wrong vector instruction will be produced: 
       vrgather.vv      v25, v25, v25
in the below test case.
>From the the vector spec, there is a rule: for any vrgather instruction, the
destination vector register group cannot overlap the source vector register
group. 

vrgather-test.ll:

declare <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(
  <vscale x 8 x i8>,
  <vscale x 8 x i8>,
  i64);

define dso_local signext i32 @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8()
nounwind {
entry:
  %0 = alloca <vscale x 8 x i8>, align 8
  %1 = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(
    <vscale x 8 x i8> undef,
    <vscale x 8 x i8> undef,
    i64 undef)
  store volatile <vscale x 8 x i8> %1, <vscale x 8 x i8>* %0, align 8

  ret i32 0
}


llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh
-verify-machineinstrs vrgather-test.ll -o vrgather-test.s

vrgather-test.s:
        .text
        .attribute      4, 16
        .attribute      5, "rv64i2p0_f2p0_d2p0_v0p10_zfh0p1"
        .file   "vrgather-test.ll"
        .globl  intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8 # -- Begin function
intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
        .p2align        2
        .type   intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8, at function
intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: #
@intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
# %bb.0:                                # %entry
        addi    sp, sp, -16
        csrr    a0, vlenb
        sub     sp, sp, a0
        vsetvli zero, a0, e8,m1,ta,mu
        vrgather.vv     v25, v25, v25
        addi    a0, sp, 16
        vs1r.v  v25, (a0)
        mv      a0, zero
        csrr    a1, vlenb
        add     sp, sp, a1
        addi    sp, sp, 16
        ret
.Lfunc_end0:
        .size   intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8,
.Lfunc_end0-intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
                                        # -- End function
        .section        ".note.GNU-stack","", at progbits

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