<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [RISCV] wrong vector register alloc in vector instruction"
   href="https://bugs.llvm.org/show_bug.cgi?id=50813">50813</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[RISCV] wrong vector register alloc  in vector instruction
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>tangxingxin1008@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>htmldeveloper@gmail.com, llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>There is a wrong vector instruction will be produced: 
       vrgather.vv      v25, v25, v25
in the below test case.
>From the the vector spec, there is a rule: for any vrgather instruction, the
destination vector register group cannot overlap the source vector register
group. 

vrgather-test.ll:

declare <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(
  <vscale x 8 x i8>,
  <vscale x 8 x i8>,
  i64);

define dso_local signext i32 @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8()
nounwind {
entry:
  %0 = alloca <vscale x 8 x i8>, align 8
  %1 = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.i64(
    <vscale x 8 x i8> undef,
    <vscale x 8 x i8> undef,
    i64 undef)
  store volatile <vscale x 8 x i8> %1, <vscale x 8 x i8>* %0, align 8

  ret i32 0
}


llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh
-verify-machineinstrs vrgather-test.ll -o vrgather-test.s

vrgather-test.s:
        .text
        .attribute      4, 16
        .attribute      5, "rv64i2p0_f2p0_d2p0_v0p10_zfh0p1"
        .file   "vrgather-test.ll"
        .globl  intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8 # -- Begin function
intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
        .p2align        2
        .type   intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8,@function
intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: #
@intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
# %bb.0:                                # %entry
        addi    sp, sp, -16
        csrr    a0, vlenb
        sub     sp, sp, a0
        vsetvli zero, a0, e8,m1,ta,mu
        vrgather.vv     v25, v25, v25
        addi    a0, sp, 16
        vs1r.v  v25, (a0)
        mv      a0, zero
        csrr    a1, vlenb
        add     sp, sp, a1
        addi    sp, sp, 16
        ret
.Lfunc_end0:
        .size   intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8,
.Lfunc_end0-intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8
                                        # -- End function
        .section        ".note.GNU-stack","",@progbits</pre>
        </div>
      </p>


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