[llvm-bugs] [Bug 47552] New: Opportunity to improve codegen for i > l && l < h

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=47552

            Bug ID: 47552
           Summary: Opportunity to improve codegen for i > l  && l < h
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: david.bolvansky at gmail.com
                CC: llvm-bugs at lists.llvm.org

bool src (int i, int l, int h)
{

  return i > l  && l < h;
}



bool tgt (int i, int l, int h)
{
  int p = i < h ? i : h;
  return l < p;
}


Clang:
src(int, int, int):                              # @src(int, int, int)
        cmp     edi, esi
        setg    cl
        cmp     esi, edx
        setl    al
        and     al, cl
        ret
tgt(int, int, int):                              # @tgt(int, int, int)
        cmp     edi, edx
        cmovl   edx, edi
        cmp     edx, esi
        setg    al
        ret



----------------------------------------
define i1 @src(i32 %0, i32 %1, i32 %2) {
%3:
  %4 = icmp sgt i32 %0, %1
  %5 = icmp slt i32 %1, %2
  %6 = and i1 %4, %5
  ret i1 %6
}
=>
define i1 @tgt(i32 %0, i32 %1, i32 %2) {
%3:
  %4 = icmp slt i32 %0, %2
  %5 = select i1 %4, i32 %0, i32 %2
  %6 = icmp sgt i32 %5, %1
  ret i1 %6
}
Transformation seems to be correct!



----------------------------------------
define i1 @src(i32 %0, i32 %1, i32 %2) {
%3:
  %4 = icmp sgt i32 %0, %1
  %5 = icmp slt i32 %1, %2
  %6 = and i1 %4, %5
  ret i1 %6
}
=>
define i1 @tgt(i32 %0, i32 %1, i32 %2) {
%3:
  %4 = icmp slt i32 %0, %2
  %5 = select i1 %4, i32 %0, i32 %2
  %6 = icmp sgt i32 %5, %1
  ret i1 %6
}
Transformation seems to be correct!


So maybe request for X86 backend? For ARM this could be useful too..

ARM8:
src(int, int, int):                              // @src(int, int, int)
        cmp     w0, w1
        cset    w8, gt
        cmp     w1, w2
        cset    w9, lt
        and     w0, w8, w9
        ret
tgt(int, int, int):                              // @tgt(int, int, int)
        cmp     w0, w2
        csel    w8, w0, w2, lt
        cmp     w8, w1
        cset    w0, gt
        ret

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