[llvm-bugs] [Bug 47830] New: miscompiling sub without nsw

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=47830

            Bug ID: 47830
           Summary: miscompiling sub without nsw
           Product: libraries
           Version: 11.0
          Hardware: Other
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: programmerjake at gmail.com
                CC: llvm-bugs at lists.llvm.org, nemanja.i.ibm at gmail.com

>From https://github.com/rust-lang/rust/issues/72023#issuecomment-707901014

I didn't actually run it on a Power processor to test, but AFAICT the bug
reduces to this:
```rust
pub fn f(a: i64, b: i64) -> u64 {
    if a < b {
        0
    } else {
        a.wrapping_sub(b) as u64
    }
}
```

generated IR:
https://rust.godbolt.org/z/GYT7oG

target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

define i64 @_ZN7example1f17h0a621b2f201f6c8fE(i64 %a, i64 %b) unnamed_addr #0
!dbg !6 {
  %_3 = icmp slt i64 %a, %b, !dbg !10
  %0 = sub i64 %a, %b
  %spec.select = select i1 %_3, i64 0, i64 %0, !dbg !11
  ret i64 %spec.select, !dbg !12
}

attributes #0 = { norecurse nounwind nonlazybind readnone uwtable
"target-cpu"="ppc64le" }
<snip>

LLVM miscompiles it assuming that `a.wrapping_sub(b)` won't have signed
overflow.

https://rust.godbolt.org/z/49fncx

Output assembly:
```
example::f:
        sub.    3, 3, 4
        isellt  3, 0, 3
        blr
        .long   0
        .quad   0
```

the `sub.` sets the condition register `CR0` based on sign of wrapped result,
not on if `r3` is less than, equal to, or greater than `r4`.

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