[llvm-bugs] [Bug 46101] New: [AMDGPU][MC][DISASSEMBLER] Some code fragments may be decoded more than once

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46101

            Bug ID: 46101
           Summary: [AMDGPU][MC][DISASSEMBLER] Some code fragments may be
                    decoded more than once
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

AMDGPU disassembler has a weird bug which may result in decoding success or
failure depending on the order of instructions being decoded.

The following sequence of bytes cannot be decoded though this is a valid GFX10
code:

    0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00

However appending a nop instruction results in successful decoding:

    0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
    0x00,0x00,0x00,0x7e

    v_writelane_b32 v255, 0, s2 ; encoding:
                                  [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
    v_nop                       ; encoding: [0x00,0x00,0x00,0x7e]

The reason for this bug is that decoder (incorrectly) assumes that 0xff is a
literal operand and consumes 4 bytes after the instruction as a literal. But
then decoder gives these bytes back thus hiding the bug and allowing subsequent
bytes be decoded as a separate instruction.

See also a relevant (but separate) bug 45193 (incorrect decoding of
v_writelane_b32).

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