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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][DISASSEMBLER] Some code fragments may be decoded more than once"
href="https://bugs.llvm.org/show_bug.cgi?id=46101">46101</a>
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<th>Summary</th>
<td>[AMDGPU][MC][DISASSEMBLER] Some code fragments may be decoded more than once
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
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<pre>AMDGPU disassembler has a weird bug which may result in decoding success or
failure depending on the order of instructions being decoded.
The following sequence of bytes cannot be decoded though this is a valid GFX10
code:
0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
However appending a nop instruction results in successful decoding:
0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
0x00,0x00,0x00,0x7e
v_writelane_b32 v255, 0, s2 ; encoding:
[0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
v_nop ; encoding: [0x00,0x00,0x00,0x7e]
The reason for this bug is that decoder (incorrectly) assumes that 0xff is a
literal operand and consumes 4 bytes after the instruction as a literal. But
then decoder gives these bytes back thus hiding the bug and allowing subsequent
bytes be decoded as a separate instruction.
See also a relevant (but separate) <a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][GFX10][DISASSEMBLER] Failure to decode valid v_writelane_b32 code"
href="show_bug.cgi?id=45193">bug 45193</a> (incorrect decoding of
v_writelane_b32).</pre>
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