[llvm-bugs] [Bug 46083] New: Missed instcombine OR optimization due to ordering of OR operands

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46083

            Bug ID: 46083
           Summary: Missed instcombine OR optimization due to ordering of
                    OR operands
           Product: tools
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: opt
          Assignee: unassignedbugs at nondot.org
          Reporter: dorit.nuzman at intel.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 23532
  --> https://bugs.llvm.org/attachment.cgi?id=23532&action=edit
Input ll which Instcombine can't optimize

The only difference between the attached inputs is the order of operands in the
OR instruction.

With the "good" ordering ("or <16 x i1> %9, %6") instcombine is able to
optimize away the OR and creates this much simplified IR:

%5 = icmp ult <16 x i32> %vec.ind, <i32 1023, i32 1023, …, i32 1023, i32 1023,
i32 1023, i32 1023>
call void @llvm.masked.store.v16i8.p3v16i8(<16 x i8> %wide.masked.load, <16 x
i8> addrspace(3)* %9, i32 1, <16 x i1> %5)


With the "bad" ordering ("or <16 x i1> %6, %9") instcombine does nothing, and
we remain with all this mask logic:

  %1 = icmp ugt <16 x i32> %vec.ind, <i32 1, i32 1, ..., i32 1, i32 1>
  %2 = icmp slt <16 x i32> %vec.ind, %broadcast.splat
  %3 = and <16 x i1> %1, %2
  %5 = icmp ult <16 x i32> %vec.ind, <i32 1023,..., i32 1023, i32 1023>
  %6 = and <16 x i1> %3, %5
  %.demorgan = and <16 x i1> %1, %2
  %8 = xor <16 x i1> %.demorgan, <i1 true, i1 true, ..., i1 true, i1 true>
  %9 = and <16 x i1> %5, %8
  %13 = or <16 x i1> %6, %9
  call void @llvm.masked.store.v16i8.p3v16i8(<16 x i8> %wide.masked.load, <16 x
i8> addrspace(3)* %14, i32 1, <16 x i1> %13)

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