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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Missed instcombine OR optimization due to ordering of OR operands"
href="https://bugs.llvm.org/show_bug.cgi?id=46083">46083</a>
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<th>Summary</th>
<td>Missed instcombine OR optimization due to ordering of OR operands
</td>
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>opt
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dorit.nuzman@intel.com
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</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>Created <span class=""><a href="attachment.cgi?id=23532" name="attach_23532" title="Input ll which Instcombine can't optimize">attachment 23532</a> <a href="attachment.cgi?id=23532&action=edit" title="Input ll which Instcombine can't optimize">[details]</a></span>
Input ll which Instcombine can't optimize
The only difference between the attached inputs is the order of operands in the
OR instruction.
With the "good" ordering ("or <16 x i1> %9, %6") instcombine is able to
optimize away the OR and creates this much simplified IR:
%5 = icmp ult <16 x i32> %vec.ind, <i32 1023, i32 1023, …, i32 1023, i32 1023,
i32 1023, i32 1023>
call void @llvm.masked.store.v16i8.p3v16i8(<16 x i8> %wide.masked.load, <16 x
i8> addrspace(3)* %9, i32 1, <16 x i1> %5)
With the "bad" ordering ("or <16 x i1> %6, %9") instcombine does nothing, and
we remain with all this mask logic:
%1 = icmp ugt <16 x i32> %vec.ind, <i32 1, i32 1, ..., i32 1, i32 1>
%2 = icmp slt <16 x i32> %vec.ind, %broadcast.splat
%3 = and <16 x i1> %1, %2
%5 = icmp ult <16 x i32> %vec.ind, <i32 1023,..., i32 1023, i32 1023>
%6 = and <16 x i1> %3, %5
%.demorgan = and <16 x i1> %1, %2
%8 = xor <16 x i1> %.demorgan, <i1 true, i1 true, ..., i1 true, i1 true>
%9 = and <16 x i1> %5, %8
%13 = or <16 x i1> %6, %9
call void @llvm.masked.store.v16i8.p3v16i8(<16 x i8> %wide.masked.load, <16 x
i8> addrspace(3)* %14, i32 1, <16 x i1> %13)</pre>
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