[llvm-bugs] [Bug 46866] New: [X86] Addresses with 32-bit index and no base register are misassembled in .code16gcc mode

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46866

            Bug ID: 46866
           Summary: [X86] Addresses with 32-bit index and no base register
                    are misassembled in .code16gcc mode
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

.code16gcc mode is a mode where the processor is in 16-bit mode but the
assembly is written using 32-bit registers. As such we are supposed to use 0x67
and 0x66 prefixes to make the processor reference 32-bit register.

If the address lacks a base register we just look at the displacement to
determine if we can use a 16-bit address mode without 0x67 or if we need to use
0x67 to switch to a 32-bit mode address. In true 16-bit address parsing we
never allow the index to be filled in without the base. But if we have a 32-bit
address we are allowed to have a 32-bit index and no base.

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