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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Addresses with 32-bit index and no base register are misassembled in .code16gcc mode"
href="https://bugs.llvm.org/show_bug.cgi?id=46866">46866</a>
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<th>Summary</th>
<td>[X86] Addresses with 32-bit index and no base register are misassembled in .code16gcc mode
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
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<p>
<div>
<pre>.code16gcc mode is a mode where the processor is in 16-bit mode but the
assembly is written using 32-bit registers. As such we are supposed to use 0x67
and 0x66 prefixes to make the processor reference 32-bit register.
If the address lacks a base register we just look at the displacement to
determine if we can use a 16-bit address mode without 0x67 or if we need to use
0x67 to switch to a 32-bit mode address. In true 16-bit address parsing we
never allow the index to be filled in without the base. But if we have a 32-bit
address we are allowed to have a 32-bit index and no base.</pre>
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