[llvm-bugs] [Bug 46650] New: {disp32} instruction modifier not supported

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46650

            Bug ID: 46650
           Summary: {disp32} instruction modifier not supported
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: thiago at kde.org
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

void f()
{
    asm volatile("{disp32} jmp 0f\n"
    "0:\n")
}

GNU assembler supports this and will generate a 32-bit displacement (near) JMP
instruction instead of the 8-bit (short) that can be encoded. Very rare
use-case, but we needed for a specific application that performs hot-patching.

Problem can be worked around using -fno-integrated-as.

FYI, full list of "pseudo prefixes" from GAS documentation:

   * '{disp8}' - prefer 8-bit displacement.

   * '{disp32}' - prefer 32-bit displacement.

   * '{load}' - prefer load-form instruction.

   * '{store}' - prefer store-form instruction.

   * '{vex}' - encode with VEX prefix.

   * '{vex3}' - encode with 3-byte VEX prefix.

   * '{evex}' - encode with EVEX prefix.

   * '{rex}' - prefer REX prefix for integer and legacy vector
     instructions (x86-64 only).  Note that this differs from the 'rex'
     prefix which generates REX prefix unconditionally.

   * '{nooptimize}' - disable instruction size optimization.

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