[llvm-bugs] [Bug 48355] New: LSR produces worse assembly than without LSR

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=48355

            Bug ID: 48355
           Summary: LSR produces worse assembly than without LSR
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: max.kazantsev at azul.com
                CC: htmldeveloper at gmail.com, llvm-bugs at lists.llvm.org

Test: test/CodeGen/X86/2020_12_02_decrementing_loop.ll

IR:

define i32 @test(i32* %p, i64 %len, i32 %x) {
entry:
  br label %loop

loop:                                             ; preds = %backedge, %entry
  %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
  %iv.next = add nsw i64 %iv, -1
  %cond_1 = icmp eq i64 %iv, 0
  br i1 %cond_1, label %exit, label %backedge

backedge:                                         ; preds = %loop
  %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next
  %loaded = load atomic i32, i32* %addr unordered, align 4
  %cond_2 = icmp eq i32 %loaded, %x
  br i1 %cond_2, label %failure, label %loop

exit:                                             ; preds = %loop
  ret i32 -1

failure:                                          ; preds = %backedge
  unreachable
}

Current asm:

LBB0_1:                                 ## %loop
                                        ## =>This Inner Loop Header: Depth=1
        subq    $1, %rax
        jb      LBB0_4
## %bb.2:                               ## %backedge
                                        ##   in Loop: Header=BB0_1 Depth=1
        cmpl    %edx, -4(%rdi,%rsi,4)
        movq    %rax, %rsi
        jne     LBB0_1

When LSR is disabled:

LBB0_1:                                 ## %loop
                                        ## =>This Inner Loop Header: Depth=1
        subq    $1, %rsi
        jb      LBB0_4
## %bb.2:                               ## %backedge
                                        ##   in Loop: Header=BB0_1 Depth=1
        cmpl    %edx, (%rdi,%rsi,4)
        jne     LBB0_1

A redundant move is generated when LSR decides to replace use of iv.next with
use of iv in the gep.

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