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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - LSR produces worse assembly than without LSR"
   href="https://bugs.llvm.org/show_bug.cgi?id=48355">48355</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>LSR produces worse assembly than without LSR
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>max.kazantsev@azul.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>htmldeveloper@gmail.com, llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Test: test/CodeGen/X86/2020_12_02_decrementing_loop.ll

IR:

define i32 @test(i32* %p, i64 %len, i32 %x) {
entry:
  br label %loop

loop:                                             ; preds = %backedge, %entry
  %iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
  %iv.next = add nsw i64 %iv, -1
  %cond_1 = icmp eq i64 %iv, 0
  br i1 %cond_1, label %exit, label %backedge

backedge:                                         ; preds = %loop
  %addr = getelementptr inbounds i32, i32* %p, i64 %iv.next
  %loaded = load atomic i32, i32* %addr unordered, align 4
  %cond_2 = icmp eq i32 %loaded, %x
  br i1 %cond_2, label %failure, label %loop

exit:                                             ; preds = %loop
  ret i32 -1

failure:                                          ; preds = %backedge
  unreachable
}

Current asm:

LBB0_1:                                 ## %loop
                                        ## =>This Inner Loop Header: Depth=1
        subq    $1, %rax
        jb      LBB0_4
## %bb.2:                               ## %backedge
                                        ##   in Loop: Header=BB0_1 Depth=1
        cmpl    %edx, -4(%rdi,%rsi,4)
        movq    %rax, %rsi
        jne     LBB0_1

When LSR is disabled:

LBB0_1:                                 ## %loop
                                        ## =>This Inner Loop Header: Depth=1
        subq    $1, %rsi
        jb      LBB0_4
## %bb.2:                               ## %backedge
                                        ##   in Loop: Header=BB0_1 Depth=1
        cmpl    %edx, (%rdi,%rsi,4)
        jne     LBB0_1

A redundant move is generated when LSR decides to replace use of iv.next with
use of iv in the gep.</pre>
        </div>
      </p>


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