[llvm-bugs] [Bug 46980] New: [AMDGPU][MC] f16 inline constants are still enabled for integer operands of several opcodes

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=46980

            Bug ID: 46980
           Summary: [AMDGPU][MC] f16 inline constants are still enabled
                    for integer operands of several opcodes
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

A recent change 5f5f566 disabled use of fp inline constants with 16-bit integer
operands. However there are several opcodes which still accept such constants:

    s_sext_i32_i16
    s_pack_lh_b32_b16
    s_pack_ll_b32_b16
    s_pack_hh_b32_b16
    v_sat_pk_u8_i16  
    v_sad_u16

I believe this should be corrected.

Also there are opcodes which operate with 8-bit and 4-bit data, for example,   
 s_sext_i32_i8. Should fp inline constants be disabled for these instructions?

qsad opcodes (v_mqsad_pk_u16_u8, v_qsad_pk_u16_u8 etc) is another interesting
case because these instructions accept u16x4 operands; it is not clear how fp
inline constants are interpreted in this context.

Any ideas?

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